Senior Verification Strategy Engineer, FPGA/SoC

AMD; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD is hiring a Senior Engineer for Vivado-like design tools verification. You will own verification methodology, simulate RTL/IP, and guide deployment across installation and licensing. You will bridge R&D with sales and customers to shape product strategy.

You will lead strategic efforts across UVM, HDL simulation, and encryption, collaborating with EDA partners and customers to drive productivity and adoption in FPGA and adaptive computing environments.

Qualifications

• Deep expertise in RTL simulation and verification with UVM, formal methods, and multi-language simulation.
• Experience shaping product roadmaps for EDA/semiconductor tools or related domains.
• Ability to translate verification challenges into product innovations and customer value.

Responsibilities

• Shape the strategic roadmap for simulation, encryption, and deployment, translating customer needs into a coherent vision.
• Drive differentiation by understanding market dynamics and customer value creation.
• Own licensing and deployment strategy end-to-end, including enterprise scalability and compliance guidance.
• Represent AMD in industry standards bodies and engage with strategic customers to influence tooling directions.

Skills

UVM

SystemVerilog

RTL simulation

HDL verification

Education

Bachelor’s / Master’s / PhD in Computer Science, Computer Engineering, or Electrical Engineering

Tools

Xcelium

Questa

Riviera

Job description

AMD is hiring a Senior Engineer for Vivado-like design tools verification. You will own verification methodology, simulate RTL/IP, and guide deployment across installation and licensing. You will bridge R&D with sales and customers to shape product strategy.

You will lead strategic efforts across UVM, HDL simulation, and encryption, collaborating with EDA partners and customers to drive productivity and adoption in FPGA and adaptive computing environments.