Senior DFT Verification Engineer for ASICs

Entrada Ventures; Palo Alto (CA); Hybrid; USD 160,000 - 230,000; Full time

Benefits offered by this job

Equity

401(k)

Meaningful equity

Job summary

Entrada Ventures is seeking a Senior DFT Verification Engineer to drive robust verification for ASIC DFT logic across planning, development, and closure. You will build scalable environments, guide test strategies, and collaborate with DFT design and manufacturing teams to deliver high-quality silicon.

The role emphasizes hands-on SystemVerilog, UVM, and modern verification workflows, plus experience with scan/ATPG, JTAG, MBIST, and tester formats.

Qualifications

• 5+ years of digital design verification experience, with at least 2 years in DFT verification.
• Proficiency in SystemVerilog and UVM-based verification methodologies.
• Experience with scripting (Python) and automation.
• Experience with industry-standard EDA tools and DFT tools.
• Knowledge of PCIe and Ethernet test sequences; MBIST/scan familiarity.

Responsibilities

• Develop, implement, and maintain RTL verification environments using UVM.
• Create and execute coverage-driven verification plans.
• Use DFT tools to create and run pre-silicon MBIST/scan tests.
• Develop directed test cases for non-vendor DFT logic.
• Analyze simulation results and debug verification issues.
• Write SystemVerilog Assertions and reusable verification components.
• Automate regression testing and enhance verification infra with Python.
• Support post-silicon test bring-up with DFT designers.

Skills

SystemVerilog

UVM

Python scripting

Digital verification

Analytical problem solving

Communication

Education

Bachelor's or Master's degree in Electrical/Computer Engineering or related field

Tools

Synopsys VCS

Mentor Questa

Cadence Xcelium

Synopsys TestMax

Siemens Tessent

Job description

Entrada Ventures is seeking a Senior DFT Verification Engineer to drive robust verification for ASIC DFT logic across planning, development, and closure. You will build scalable environments, guide test strategies, and collaborate with DFT design and manufacturing teams to deliver high-quality silicon.

The role emphasizes hands-on SystemVerilog, UVM, and modern verification workflows, plus experience with scan/ATPG, JTAG, MBIST, and tester formats.