Senior ASIC Verification Engineer: Testbench Architect & Coverage Lead

Broadcom Inc.; San Jose (CA); Hybrid; USD 144,000 - 230,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision benefits

401K with match

ESPP program

Job summary

Broadcom Inc. in San Jose, CA is seeking an experienced IC Verification Engineer to architect and implement scalable testbenches, drive verification plans across Block/Core/SOC, and develop functional coverage.

The role requires deep SystemVerilog expertise, UVM/VMM, and a track record of completing ASIC projects from architecture to tape-out, plus mentoring teammates and leading verification strategy reviews.

Qualifications

• Bachelor's degree in Electrical/Electronics or equivalent with 12+ years' experience.
• Or Master's degree in Electrical/Electronics or equivalent with 10+ years' experience.
• 10+ years of experience in developing complex verification environments.
• Full ASIC cycle experience from architecture to tapeout with focus on verification.
• Proficient in SystemVerilog and verification methodologies (UVM/VMM).
• Good debugging skills and understanding of complex designs.
• Understanding PCI Express or similar multi-layered protocol.

Responsibilities

• Architect and develop scalable testbench environments using verification methodologies.
• Drive test plans for features across Block/Core/SOC and write functional coverage.
• Create pseudo-random tests to achieve full functional coverage and closure.
• Debug regression failures and improve tests to close coverage gaps.
• Collaborate with team and mentor junior engineers.
• Lead verification strategy documentation and conduct design reviews.
• Improve driver verification quality and efficiency.

Skills

SystemVerilog

UVM

VMM

Test plans

Debugging

Mentor juniors

ASIC verification

Education

Bachelor's degree in Electrical/Electronics

Master's degree in Electrical/Electronics

Tools

Python

Perl

Makefiles

Job description

Broadcom Inc. in San Jose, CA is seeking an experienced IC Verification Engineer to architect and implement scalable testbenches, drive verification plans across Block/Core/SOC, and develop functional coverage.

The role requires deep SystemVerilog expertise, UVM/VMM, and a track record of completing ASIC projects from architecture to tape-out, plus mentoring teammates and leading verification strategy reviews.