RTL Integration Engineer | SoC Debug & CDC Expert

Broadcom Inc.; San Jose (CA); On-site; USD 143,800 - 230,000; Full time

Benefits offered by this job

Discretionary bonus

Equity grant

Annual equity awards

Medical benefits

401K with matching

ESPP

EAP

Paid holidays

Job summary

Broadcom Inc. in California seeks a senior RTL/SoC verification engineer to perform IP integration, test and debug at the SoC level, and create RTL designs with linting. The role includes CDC/RDC analysis for RTL and gate-level designs, plus synthesis, palladium modeling and STA support.

Candidates should have expertise in UVM and SystemVerilog, GLS, zero-delay and SDF simulations, and strong debugging and communication skills. A Bachelor's degree with 12+ years experience is required.

Qualifications

• Extensive knowledge of implementation, synthesis, and timing issues.
• Strong understanding of UVM and SystemVerilog.
• Deep familiarity with zero-delay and SDF simulations; ability to debug failures effectively.
• Proven experience in gate-level simulation (GLS).
• Familiarity with CDC analysis for RTL and gate-level designs.
• Experience with simulation tools such as NCSim and VCS.
• Ability to work independently and with a global team; quick learner and adaptable.
• Excellent communication skills.

Responsibilities

• Perform IP integration and IP test/debug mode verification at the SoC level.
• Create RTL designs and perform linting.
• Execute CDC and RDC analysis for RTL and gate-level designs.
• Handle synthesis, palladium modeling, and STA support.
• Apply strong debugging skills to diagnose and resolve issues.

Skills

UVM & SystemVerilog

Gate-level simulations

CDC analysis

SDF/Zero-delay

NCSim / VCS

Debugging

Communication

Education

Bachelor's + 12+ years

Tools

RTL tooling

Synthesis

Job description

Broadcom Inc. in California seeks a senior RTL/SoC verification engineer to perform IP integration, test and debug at the SoC level, and create RTL designs with linting. The role includes CDC/RDC analysis for RTL and gate-level designs, plus synthesis, palladium modeling and STA support.

Candidates should have expertise in UVM and SystemVerilog, GLS, zero-delay and SDF simulations, and strong debugging and communication skills. A Bachelor's degree with 12+ years experience is required.