ASIC/SoC Design Verification Engineer

INA Solution; United States; Remote; USD 120,000 - 160,000; Full time

Job summary

INA Solution is seeking an experienced SoC Verification Engineer with hands-on ASIC verification and end-to-end UVM expertise. This remote, full-time role focuses on block-level verification for complex designs.

You will develop and maintain UVM testbenches, run directed and constrained-random tests, analyze waveforms, and collaborate with customer engineering teams and project leads.

Qualifications

• 6–10+ years of hands-on ASIC verification experience.
• End-to-end UVM experience from scratch, including testbench infrastr., sequences, agents, scoreboards, debugging, and coverage.
• Strong proficiency in SystemVerilog and UVM.
• Experience verifying complex digital designs, preferably networking silicon, switches, NICs, or high‑performance interconnect ASICs.
• Strong waveform analysis, root-cause analysis, and regression debugging skills.

Responsibilities

• Own block-level verification for complex design blocks.
• Develop and maintain UVM testbenches, components, scoreboards, and functional coverage models from scratch.
• Execute directed and constrained-random testing and drive coverage closure.
• Debug failures, analyze waveforms, and perform regression triage.
• Collaborate with customer engineering teams and internal project leads.

Skills

ASIC verification

SystemVerilog

UVM

Debugging

Regression testing

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

Location: Remote

Job Type: Full Time

Job Description:

We are looking for an experienced SoC Verification Engineer with strong hands-on ASIC verification experience and end-to-end UVM expertise.

Must-Have Requirements:

• 6–10+ years of hands-on ASIC verification experience.
• End-to-end UVM experience from scratch, including testbench infrastructure, sequences, agents, scoreboards, debugging, and coverage closure.
• Strong proficiency in SystemVerilog and UVM.
• Experience verifying complex digital designs, preferably networking silicon, switches, NICs, or high-performance interconnect ASICs.
• Strong waveform analysis, root-cause analysis, and regression debugging skills.

Preferred Skills:

• Protocol verification experience with Ethernet, UCIe 2.0, or PCIe Gen 4/5/6.
• Experience with Synopsys VCS, Cadence Xcelium, or Mentor Questa simulators.

Key Responsibilities:

• Own block-level verification for complex design blocks.
• Develop and maintain UVM testbenches, components, scoreboards, and functional coverage models from scratch.
• Execute directed and constrained-random testing and drive coverage closure.
• Debug failures, analyze waveforms, and perform regression triage.
• Collaborate with customer engineering teams and internal project leads.