IC Verification Engineer — Test Benches & Coverage

Broadcom; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

401(k) with company match

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Paid holidays, sick leave and vacation

Job summary

Broadcom in San Jose, CA seeks an experienced verification engineer to develop test plans for Block/Core/SOC, architect reusable test benches, and create pseudo-random tests to deliver full functional coverage.

The role requires advanced SystemVerilog, UVM/VMM/OVM proficiency, strong OO programming, and deep PCIe protocol knowledge. You will debug regressions, document verification strategy, and drive quality and efficiency across the verification flow.

Qualifications

• Bachelor's degree in Electrical Engineering or related field with 8+ years of experience, or Master's with 6+ years.
• 6+ years of experience in writing and debugging complex test benches.
• Deep understanding of verification: test benches, test plans and pseudo-random tests.

Responsibilities

• Develop test plans for Block/Core/SOC features and write functional coverage.
• Architect and develop scalable, reusable test benches using verification methodology.
• Build pseudo-random tests to verify and achieve full functional coverage.
• Debug regression failures and analyze functional coverage gaps.
• Lead verification strategy documentation and reviews with design/architecture.
• Drive improvements in verification quality and efficiency.

Skills

SystemVerilog

Testbench Development

Verification Methodologies

OO Programming

PCIe Protocol

Education

Bachelor's in Electrical Engineering or related

Master's in Electrical Engineering or related

Tools

UVM

VMM

OVM

Job description

Broadcom in San Jose, CA seeks an experienced verification engineer to develop test plans for Block/Core/SOC, architect reusable test benches, and create pseudo-random tests to deliver full functional coverage.

The role requires advanced SystemVerilog, UVM/VMM/OVM proficiency, strong OO programming, and deep PCIe protocol knowledge. You will debug regressions, document verification strategy, and drive quality and efficiency across the verification flow.