Senior SystemVerilog RTL Design Engineer - 5nm SoC

Broadcom Inc.; Fort Collins (CO); On-site; USD 101,000 - 162,000; Full time

Benefits offered by this job

Medical plans

Dental plan

Vision plan

401K

ESPP

EAP

Paid holidays

Vacation and sick leave

Job summary

Broadcom Inc. is seeking an experienced SoC RTL engineer to deliver SystemVerilog RTL at advanced nodes (5nm and below) with a focus on PPA optimization, CDC/RDC analysis and low-power design.

You will drive designs from specification through timing closure and hand-off to physical design. You will collaborate with Architecture, Verification and Physical Design teams to mitigate risks, meet milestones and contribute to high-speed SerDes, LPDDR/DDR and/or HBM protocols in a dynamic, equitable

Qualifications

• BSEE required; MSEE/PhD preferred.
• 5+ years of industry experience with SoC integration, high-speed SerDes, LPDDR/DDR, and/or HBM protocols preferred.
• Experience with advanced process nodes (5nm and below) and RTL design optimization.

Responsibilities

• Lead designs from spec to timing closure and hand-off to physical design.
• Collaborate with Architecture, Verification, and Physical Design teams to mitigate risks and hit milestones.
• Demonstrate high SystemVerilog proficiency.
• Deliver high-quality SystemVerilog RTL with PPA optimization, CDC/RDC analysis, and low-power design techniques.

Skills

SystemVerilog RTL

PPA optimization

CDC analysis

RDC analysis

Low-power design

Education

BSEE

MSEE/PhD preferred

Job description

Broadcom Inc. is seeking an experienced SoC RTL engineer to deliver SystemVerilog RTL at advanced nodes (5nm and below) with a focus on PPA optimization, CDC/RDC analysis and low-power design.

You will drive designs from specification through timing closure and hand-off to physical design. You will collaborate with Architecture, Verification and Physical Design teams to mitigate risks, meet milestones and contribute to high-speed SerDes, LPDDR/DDR and/or HBM protocols in a dynamic, equitable