Senior UVM Design Verification Engineer for SoC/ASIC

Broadcom; San Jose (CA); On-site; USD 101,000 - 162,000; Full time

Benefits offered by this job

Discretionary annual bonus

New hire equity grant

Annual equity awards

Medical, dental and vision

401(K) with company match

Employee Stock Purchase Program (ESPP)

Paid holidays

Paid time off

Job summary

Broadcom in San Jose seeks an experienced Design Verification engineer with a strong background in UVM testbenches for large-scale SoCs. You will own the verification environment from spec to timing closure and coordinate with Architecture, Verification, and Physical Design teams.

The ideal candidate has a BSEE, 5+ years in SoC integration and testbench setup, and a proven track record of delivering high-quality designs on schedule. A discretionary bonus and equity opportunities are included.

Qualifications

• BSEE required; advanced degree preferred.
• 5+ years of industry experience in SoC integration and UVM test benches.

Responsibilities

• Take designs from spec through timing closure and hand-off to physical design.
• Collaborate with Architecture, Verification and Physical Design teams to meet milestones.
• Maintain high proficiency in UVM.

Skills

UVM

Design Verification

Testbench setup

Education

BSEE

MSEE or PhD

Job description

Broadcom in San Jose seeks an experienced Design Verification engineer with a strong background in UVM testbenches for large-scale SoCs. You will own the verification environment from spec to timing closure and coordinate with Architecture, Verification, and Physical Design teams.

The ideal candidate has a BSEE, 5+ years in SoC integration and testbench setup, and a proven track record of delivering high-quality designs on schedule. A discretionary bonus and equity opportunities are included.