Senior SoC Verification Engineer - UVM/SystemVerilog Pro

VDart; Chesterbrook (PA); On-site; USD 120,000 - 170,000; Full time

Job summary

VDart seeks an experienced ASIC verification engineer with 6–10+ years of hands-on ASIC verification experience. You will own block-level verification, develop verification components from scratch, and drive coverage closure using SystemVerilog and UVM.

You will work with customers and internal leads to ensure alignment with the top-level testbench infrastructure. Expertise in SystemVerilog/UVM and testbench development, plus hands-on protocol knowledge (Ethernet, PCIe, UCIe 2.0) is required.

Qualifications

• 6 to 10+ years of hands-on ASIC verification experience in complex digital designs.
• Expert-level SystemVerilog and UVM, with a proven history of developing testbenches and components from scratch.
• Hands-on verification experience with one or more high-speed protocols such as Ethernet, PCIe, or similar.

Responsibilities

• Block-Level Verification Ownership: take technical ownership of verifying 4-5 blocks per project.
• Testbench & Component Development: build and maintain verification components, sequences, agents, scoreboards, and coverage models from scratch.
• Verification Execution: run directed and constrained-random tests, debug failures, and drive coverage closure.
• Protocol Application: apply knowledge of high-speed protocols (Ethernet, PCIe, UCIe 2.0) for architectural verification.
• Collaboration: interface with customer teams and internal leads to align with top-level testbenches.
• Debugging & Triage: perform waveform analysis, protocol debugging, root-cause analysis, and regression triage.

Skills

SystemVerilog

UVM

Testbench development

Constrained-random testing

Waveform analysis

Debugging

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

VDart seeks an experienced ASIC verification engineer with 6–10+ years of hands-on ASIC verification experience. You will own block-level verification, develop verification components from scratch, and drive coverage closure using SystemVerilog and UVM.

You will work with customers and internal leads to ensure alignment with the top-level testbench infrastructure. Expertise in SystemVerilog/UVM and testbench development, plus hands-on protocol knowledge (Ethernet, PCIe, UCIe 2.0) is required.