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Broadcom in San Jose seeks an experienced Design Verification engineer with a strong background in UVM testbenches for large-scale SoCs. You will own the verification environment from spec to timing closure and coordinate with Architecture, Verification, and Physical Design teams.
The ideal candidate has a BSEE, 5+ years in SoC integration and testbench setup, and a proven track record of delivering high-quality designs on schedule. A discretionary bonus and equity opportunities are included.
The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs.
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