Senior ASIC Verification Engineer – SystemVerilog/UVM

Broadcom; Broomfield (CO); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grant

401(k) participation

Job summary

Broadcom is seeking a Design Verification Engineer to model and verify complex digital and mixed‑signal IP blocks for ASICs. You will define verification plans, build test benches, analyze coverage, and drive debug across RTL and gate‑level contexts.

The role may involve emulation and FPGA prototyping, and adoption of advanced verification methodologies. The candidate should have SystemVerilog, UVM, and experience with assertions, random/directed test cases, and scripting.

Qualifications

• 12+ years of verification experience for digital and mixed-signal circuits.

Responsibilities

• Define verification plans and environment architecture.

Skills

SystemVerilog

UVM

Test benches

Coverage

Perl/Python

Git

EMULATION

Education

BS in Electrical/Computer Engineering

MS in Electrical/Computer Engineering

Tools

Synopsys

Cadence

Mentor

Palladium/Veloce/Zebu

Xilinx

Tessent

Job description

Broadcom is seeking a Design Verification Engineer to model and verify complex digital and mixed‑signal IP blocks for ASICs. You will define verification plans, build test benches, analyze coverage, and drive debug across RTL and gate‑level contexts.

The role may involve emulation and FPGA prototyping, and adoption of advanced verification methodologies. The candidate should have SystemVerilog, UVM, and experience with assertions, random/directed test cases, and scripting.