Senior to Principal Physical Design Engineer – ASIC SoCs

MaC VC; Austin (TX); On-site; USD 123,000 - 250,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking highly motivated Physical Design Engineers across multiple levels for its ASIC implementation team, including floorplanning, PnR, CTS, timing closure, and power optimization.

You will collaborate with architecture, RTL, DFT, and CAD teams to deliver high-performance SiP and SoC blocks, from synthesis to tapeout. The role supports GPUs, multimedia, AI, compute, connectivity, modem, and DDR/IP blocks across fabric levels.; candidates may advance from Engineer

Qualifications

• Bachelors or higher in Electrical/Computer Engineering, or a related field.
• Experience with digital ASIC physical implementation methodologies.
• Understanding of PPA tradeoffs and timing analysis.
• Experience in Linux/Unix environments and scripting (Python, Tcl, etc.).
• Experience with complete Physical Design Flow from synthesis through tapeout (preferred).
• Strong communication and collaboration skills.

Responsibilities

• Lead or contribute to physical design implementation for ASIC/SoC blocks.
• Perform floorplanning, placement, CTS, routing, and timing analysis.
• Drive power planning, clock tree synthesis, and signoff activities.
• Develop automation scripts to improve design productivity.
• Collaborate with Architecture, RTL, DFT, CAD, and product teams to deliver tapeouts.

Skills

Physical design

Floorplanning

Clock Tree Synthesis

Timing closure

Automation & scripting

Signal integrity

Power optimization

Design verification

Education

Bachelor's degree in Electrical/Computer Engineering or related field

Master's degree in related field

PhD in related field (optional)

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Job description

Qualcomm Technologies, Inc. is seeking highly motivated Physical Design Engineers across multiple levels for its ASIC implementation team, including floorplanning, PnR, CTS, timing closure, and power optimization.

You will collaborate with architecture, RTL, DFT, and CAD teams to deliver high-performance SiP and SoC blocks, from synthesis to tapeout. The role supports GPUs, multimedia, AI, compute, connectivity, modem, and DDR/IP blocks across fabric levels.; candidates may advance from Engineer