Principal Physical Design Engineer – SoC Tapeout

MaC VC; San Diego (CA); On-site; USD 123,000 - 250,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego, CA seeks multiple levels of highly motivated Physical Design Engineers to join our ASIC implementation team.

You will contribute to development and execution of physical design methodologies for complex, high‑performance designs, collaborating with architecture, RTL, DFT, CAD, and product teams to deliver from synthesis to tapeout. The ideal candidate has expertise in physical implementation, timing closure, and low‑power design techniques, with

Qualifications

• Bachelor's / Master / PhD with ASIC design experience or related work.
• Experience with digital ASIC physical implementation methodologies.
• Proficiency in Linux/Unix environments and scripting.
• Strong analytical, problem‑solving, and debugging skills.

Responsibilities

• Lead physical design tasks including floorplanning, place & route, CTS, routing, timing and verification.
• Drive timing closure, power optimization, and design convergence.
• Develop automation and scripting to improve design productivity.
• Mentor junior engineers and collaborate with cross‑functional teams.

Skills

Leadership

Mentoring

Problem solving

Collaboration

Education

Bachelor's degree

Master's degree

PhD

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

MMMC

UPF

Python

Shell

Tcl

Perl

Linux/Unix

Job description

Qualcomm Technologies, Inc. in San Diego, CA seeks multiple levels of highly motivated Physical Design Engineers to join our ASIC implementation team.

You will contribute to development and execution of physical design methodologies for complex, high‑performance designs, collaborating with architecture, RTL, DFT, CAD, and product teams to deliver from synthesis to tapeout. The ideal candidate has expertise in physical implementation, timing closure, and low‑power design techniques, with