Senior ASIC Physical Design Engineer

QUALCOMM, Inc.; Austin (TX); On-site; USD 146,000 - 218,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an ASIC Engineer in the Engineering Group to define, model, design (digital and/or analog), optimize, verify, validate, implement and document IP for high-performance low-power products.

You will collaborate across software and hardware teams to meet system requirements and deliver world-class ASICs. The role requires 4+ years ASIC design/verification experience (Bachelor's) or 2+ years with a PhD, and may involve leadership interactions with senior staff.

Qualifications

• Bachelor's degree with 4+ years ASIC design/verification experience; master's/PhD with fewer years acceptable.
• Preferred: advanced degrees with 6+ years ASIC-related work and leadership exposure.
• Experience with architecture/design tools and scripting languages.

Responsibilities

• Define, model, design, optimize, verify, validate, implement and document IP for high-performance ASIC/SoC.
• Create architectures, circuit specs and system simulations from requirements.
• Collaborate with software/hardware teams to meet system and customer needs.
• Evaluate process flow from design to layout, timing and power; guide complex blocks.
• Produce detailed technical documentation for EDA/IP/ASIC projects.

Skills

ASIC design

Verification

Validation

Integration

IP development

Scripting tools

Education

Bachelor's degree in Science/Engineering or related field

Master's degree in Science/Engineering or related field

PhD in Science/Engineering or related field

Tools

RTL to GDS Flow

Virtuoso

Job description

Qualcomm Technologies, Inc. is seeking an ASIC Engineer in the Engineering Group to define, model, design (digital and/or analog), optimize, verify, validate, implement and document IP for high-performance low-power products.

You will collaborate across software and hardware teams to meet system requirements and deliver world-class ASICs. The role requires 4+ years ASIC design/verification experience (Bachelor's) or 2+ years with a PhD, and may involve leadership interactions with senior staff.