Senior SystemVerilog RTL Design Engineer, 5nm+ | Equity

Broadcom; San Jose (CA); Sur place; USD 122 000 - 195 000; Plein temps

Résumé du poste

Broadcom is seeking a senior SystemVerilog RTL engineer in San Jose, CA to drive designs from specification through timing closure and physical hand-off. You will work with Architecture, Verification, and Physical Design to mitigate risks and ensure milestones are met, applying advanced RTL techniques for 5nm and below processes.

The role requires a strong background in SystemVerilog, PPA optimization, CDC/RDC analysis, and low-power design.

Qualifications

• BSEE required; MSEE/PhD preferred.
• 8+ years of industry experience focused on SoC integration, LPDDR5/6, DDR4/5 and/or high-speed SerDes or HBM protocols is highly preferred.

Responsabilités

• Operate with autonomy from initial specification to timing closure and physical design hand-off.
• Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure milestones.
• High proficiency in SystemVerilog.
• Deliver high-quality SystemVerilog RTL in advanced process nodes (5nm and below) with PPA optimization, CDC analysis, and low-power design techniques.

Connaissances

SystemVerilog

RTL design

PPA optimization

CDC analysis

RDC

low-power design

Formation

BSEE

MSEE

PhD preferred

Description du poste

Broadcom is seeking a senior SystemVerilog RTL engineer in San Jose, CA to drive designs from specification through timing closure and physical hand-off. You will work with Architecture, Verification, and Physical Design to mitigate risks and ensure milestones are met, applying advanced RTL techniques for 5nm and below processes.

The role requires a strong background in SystemVerilog, PPA optimization, CDC/RDC analysis, and low-power design.