Senior RTL Design Engineer - Networking ASICs + Equity

Broadcom; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Job summary

Broadcom in San Jose seeks a Logic Design Engineer to contribute to high‑performance Ethernet switch ASICs. You will implement RTL in Verilog and participate in the full design lifecycle from architecture to timing convergence and ECOs.

Required is a BS in electrical/computer engineering (MS preferred) and 5+ years of digital design on networking ASICs, with strong Verilog RTL and debugging skills, plus the ability to work independently.

Qualifications

• B.S. in electrical engineering, computer engineering, computer science, or equivalent.
• B.S. with 8 years of experience, or M.S with 5 years of experience in digital design on multiple networking ASICs.
• 5+ years of experience in verilog based rtl design or verification, in deep submicron technologies.
• Familiarity with Ethernet and other networking protocols.

Responsibilities

• Participate in full program design lifecycle from architecture to RTL implementation, unit verification, timing convergence and ECOs.
• Write efficient and elegant RTL for implementing components of complex networking ASICs.
• Collaborate with cross‑functional teams to ensure design meets performance and power targets.

Skills

Verilog RTL design

Digital design

Networking ASICs

Troubleshooting

Education

B.S. in Electrical/Computer Engineering or CS

MS or 8+ years experience

Tools

Python

Perl

Timing analysis

Job description

Broadcom in San Jose seeks a Logic Design Engineer to contribute to high‑performance Ethernet switch ASICs. You will implement RTL in Verilog and participate in the full design lifecycle from architecture to timing convergence and ECOs.

Required is a BS in electrical/computer engineering (MS preferred) and 5+ years of digital design on networking ASICs, with strong Verilog RTL and debugging skills, plus the ability to work independently.