Senior Design Verification Architect (SystemVerilog/UVM)

Renesas Electronics Corp.; Town of Texas (WI); On-site; USD 120,000 - 160,000; Full time

Job summary

Renesas Electronics is seeking a Principal Design Verification Engineer to provide technical leadership for verifying next-generation semiconductor memory interfaces and data buffer silicon. The role centers on defining and executing verification strategy at block and system levels, and owning verification from planning through signoff.

You will architect and maintain SystemVerilog/UVM testbenches, drive coverage closure, and mentor engineers while collaborating with RTL/design teams to ensure

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Extensive experience in semiconductor design verification with ownership of complex verification.
• Expert-level proficiency with SystemVerilog.
• Significant hands-on experience with UVM, including development and optimization of UVM-based environments.
• Experience defining verification strategies and developing verification plans from design/specifications.
• Strong experience with functional verification, constrained-random testing, coverage, debugging, and closure.

Responsibilities

• Lead verification strategy and execution for complex designs at the block and system level.
• Define verification methodologies, test plans, coverage strategies, and environments.
• Architect, develop, maintain, and optimize SystemVerilog/UVM testbenches and environments.
• Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure.
• Own verification for assigned blocks/features from planning through signoff.
• Collaborate with RTL/design engineers to ensure verifiability and performance.
• Analyze specs, design, and verification results to identify gaps and issues.
• Drive debugging and resolution of complex verification failures.
• Develop scalable reusable verification components and best practices.
• Lead improvements in verification efficiency and quality.

Skills

SystemVerilog

UVM

Semiconductor verification

Mentoring

Education

Bachelor's or Master's in EE/CE/CS

Tools

DDR memory interfaces

DDR4/DDR5

Memory controllers

High-speed interfaces

Job description

Renesas Electronics is seeking a Principal Design Verification Engineer to provide technical leadership for verifying next-generation semiconductor memory interfaces and data buffer silicon. The role centers on defining and executing verification strategy at block and system levels, and owning verification from planning through signoff.

You will architect and maintain SystemVerilog/UVM testbenches, drive coverage closure, and mentor engineers while collaborating with RTL/design teams to ensure