Senior DFT Architect - Lead Test Strategy for AI/SoC

TylSemi, Inc.; San Jose (CA); On-site; USD 238,000 - 286,000; Full time

Job summary

TylSemi, Inc. in San Jose, CA, is seeking an experienced DFT Architect to lead design-for-test strategy and implementation for complex ASIC/SOC designs across advanced nodes.

You will drive end-to-end DFT architecture including scan, MBIST, compression, boundary scan, and at-speed test methodologies while collaborating with RTL, Physical Design, Verification, and Product Engineering teams to achieve high test coverage and smooth silicon bring-up.

Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
• 10+ years of ASIC/SOC DFT implementation and architecture.
• Expertise in scan, ATPG, MBIST, JTAG, compression, and low-power DFT.
• Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent.
• Strong understanding of RTL design, timing, physical design constraints, and silicon debug.
• Experience with advanced technology nodes and large SOC integration.
• Strong scripting and automation skills using Tcl, Python, Perl, or Shell.
• Excellent leadership, problem-solving, and cross-functional collaboration skills.

Responsibilities

• Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs.
• Lead implementation of scan insertion, ATPG, MBIST, LBIST, boundary scan, and test compression methodologies.
• Drive DFT planning and integration aligned with power, timing, area, and test coverage goals.
• Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for seamless DFT integration and signoff.
• Analyze and resolve DFT-related timing, routing, and testability challenges.
• Support silicon bring-up, debug, diagnosis, yield analysis, and production test optimization.
• Develop and enhance DFT automation flows, methodologies, and reusable infrastructure.
• Mentor junior engineers and provide technical leadership across projects.

Skills

DFT architecture

ATPG/scan/MBIST/JTAG/compression

RTL design & timing

Scripting (Tcl, Python, Perl)

Leadership & collaboration

Education

Bachelor’s or Master’s degree in Electronics / related field

Tools

Siemens Tessent

Synopsys DFT Compiler/TestMAX

Job description

TylSemi, Inc. in San Jose, CA, is seeking an experienced DFT Architect to lead design-for-test strategy and implementation for complex ASIC/SOC designs across advanced nodes.

You will drive end-to-end DFT architecture including scan, MBIST, compression, boundary scan, and at-speed test methodologies while collaborating with RTL, Physical Design, Verification, and Product Engineering teams to achieve high test coverage and smooth silicon bring-up.