Sr. Staff Design Verification Engineer

AMD; San Jose (CA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

AMD Benefits at a glance

Job summary

AMD is seeking a Senior Staff Silicon Design Engineer to join our Silicon Design Engineering team in San Jose, hybrid work model. You will drive DFT architecture, implementation, and bring-up for complex SoCs, collaborating with architecture, design, verification, and manufacturing to ensure testability and high-quality silicon.

You will mentor engineers, influence DFT strategy, and lead cross-functional initiatives across RTL, physical design, and product engineering to deliver industry-leading

Qualifications

• Design-for-Test (DFT) architecture, implementation, and bring-up for complex SoCs.
• RTL design and integration using Verilog/SystemVerilog.
• Experience with high-speed interfaces and complex IPs (HBM, D2D, SerDes, PCIe, memory subsystems).
• Understanding of VLSI design principles, DDA methodologies, and IC development processes.
• Familiarity with floorplanning, synthesis, place-and-route, timing closure, STA.

Responsibilities

• Define, implement, and verify DFT architectures and test features for complex SoCs and IP subsystems.
• Drive scan insertion, ATPG generation, and test methodology development to meet quality targets.
• Develop and execute gate-level simulation strategies for ATPG pattern validation and test readiness.
• Analyze test coverage, diagnose gaps, and drive improvements in test quality and manufacturability.
• Partner with design, verification, physical design, and product engineering to ensure DFT implementation across the development cycle.
• Support silicon bring-up, manufacturing test, failure analysis, and yield improvement activities.
• Develop scalable DFT methodologies, automation solutions, and best practices across projects.
• Provide technical leadership and mentorship across the organization.

Skills

DFT architecture

Verilog/SystemVerilog

HBM/PCIe

VLSI design

EDA tools

UVM/OVM

Scripting (Perl/Tcl/Python)

Technical leadership

Communication

Mentoring

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys DFT Compiler

TestMAX

PrimeTime

VCS

Cadence tool suites

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

AMD is seeking a highly motivated Senior Staff Silicon Design Engineer to join our Silicon Design Engineering organization and contribute to the development of next-generation high-performance computing, AI, and graphics products. In this role, you will be a key contributor to the front-end design and DFT methodology team, driving design-for-test architecture, implementation, and silicon validation across complex SoCs. You will collaborate closely with architecture, design, verification, physical design, product engineering, and manufacturing teams to ensure robust testability, high-quality silicon execution, and first-pass silicon success. This role offers the opportunity to influence DFT strategy and methodology while helping deliver industry-leading products to market.

The Person

The ideal candidate is a seasoned silicon engineer with strong expertise in Design-for-Test (DFT) architecture, implementation, and bring-up for complex semiconductor devices. You are a technical leader who thrives in a highly collaborative environment and can drive cross-functional efforts spanning design, verification, physical implementation, and product engineering. You possess excellent analytical and problem-solving skills, demonstrate attention to detail, and are comfortable owning critical technical deliverables throughout the product lifecycle. You have a track record of independently driving complex projects, mentoring junior engineers, and influencing technical decisions across teams.

Key Responsibilities

• Define, implement, and verify DFT architectures and test features for complex SoCs and IP subsystems.
• Drive scan insertion, ATPG generation, and test methodology development to achieve aggressive quality and coverage targets.
• Develop and execute gate-level simulation strategies for ATPG pattern validation and test readiness.
• Analyze test coverage, diagnose coverage gaps, and drive improvements in test quality, manufacturability, and test cost reduction.
• Partner with design, verification, physical design, and product engineering teams to ensure successful DFT implementation throughout the development cycle.
• Support silicon bring-up, manufacturing test execution, failure analysis, and yield improvement activities.
• Contribute to the development and deployment of scalable DFT methodologies, automation solutions, and best practices across projects.
• Provide technical leadership, mentorship, and guidance to engineers across the organization.

Preferred Experience

• Strong understanding of the complete ASIC/SoC development flow, from RTL architecture through physical implementation and silicon bring-up.
• Strong RTL design and integration experience using Verilog and SystemVerilog.
• Experience working with high-speed interfaces and complex IPs such as HBM, Die-to-Die (D2D), SerDes, PCIe, and memory subsystems.
• Deep understanding of VLSI design principles, Design Automation methodologies, and IC development processes.
• Working knowledge of physical design concepts including floorplanning, synthesis, place-and-route, timing closure, and Static Timing Analysis (STA).
• Hands-on experience with industry-standard EDA tools such as Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, and Cadence tool suites.
• Experience with UVM/OVM verification methodologies, testbench development, BFMs, simulation environments, and debug workflows.
• Proven experience implementing DFT solutions for large-scale SoCs, including scan, compression, MBIST, LBIST, boundary scan, and related test technologies.
• Familiarity with FPGA architectures and prototyping methodologies is a plus.
• Strong scripting and automation skills using Perl, Tcl, Shell, Python, or similar languages.
• Demonstrated ability to independently drive technical initiatives and solve complex engineering challenges.
• Excellent written and verbal communication skills, with the ability to effectively collaborate across geographically distributed teams.
• Proven ability to mentor engineers and contribute to technical leadership within an organization.

Academic Credentials

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

LOCATION

San Jose, CA (Hybrid)

Benefits offered are described: AMD benefits at a glance.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.