Senior Staff GPU Feasibility & PPA Architect

Samsung Electronics Perú; Austin (TX); On-site; USD 180,000 - 270,000; Full time

Benefits offered by this job

Medical, dental, vision

Life insurance

401(k)

Onsite lunch

Tuition assistance

Paid time off

Student loan program

Wellness incentives

Employee purchase program

Job summary

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) seek a Senior Staff Physical Design Feasibility Engineer to drive PPA for ASIC and interposer designs. You will lead feasibility from floor planning through tape-out and sign-off, collaborating with RTL and architects to optimize GPU designs and meet timing, power, and area targets.

You will also guide RTL/netlist-to-GDS flows, automate flows with TCL/Perl/Shell/Python, and deliver high-quality, scalable

Qualifications

• 10+ years of experience in ASIC/SoC design or related field.
• Solid understanding of SOC/ASIC design flow and P&R processes.
• Knowledge of Verilog and timing constraints.

Responsibilities

• Lead feasibility and optimization of complex ASIC/interposer designs from floor planning to tape-out and sign-off.
• Collaborate with RTL, architects, and design teams to drive architectural and RTL improvements for PPA targets.
• Ensure synthesis, floorplanning, place & route meet PPA goals and functional requirements.
• Deliver RTL/netlist to GDS flow and automate design flows with TCL/Perl/Shell/Python.
• Communicate clearly across teams and manage high-quality deliverables.

Skills

PPA optimization

GPU architecture knowledge

Scripting (TCL, Perl, Python)

Team collaboration

Communication

Education

Bachelor's degree in CS/CE

Master’s degree

PhD

Tools

Synthesis tools

Floorplanning tools

Place & Route tools

GDS flow

Job description

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) seek a Senior Staff Physical Design Feasibility Engineer to drive PPA for ASIC and interposer designs. You will lead feasibility from floor planning through tape-out and sign-off, collaborating with RTL and architects to optimize GPU designs and meet timing, power, and area targets.

You will also guide RTL/netlist-to-GDS flows, automate flows with TCL/Perl/Shell/Python, and deliver high-quality, scalable