Senior GPU Physical Design Engineer – Floorplanning & PPA

Samsung Electronics Perú; Austin (TX); On-site; USD 180,000 - 270,000; Full time

Job summary

Samsung Austin Research and Development Center seeks a Senior Staff GPU Physical Design Engineer to shape full-chip and block-level implementation, focusing on top-level floorplanning, routing, and signoff for high-performance GPU IP. You will advance methodology, automate flows, and collaborate across architecture, RTL, and system teams.

With 11+ years in physical design or 7+ with a PhD, you will mentor engineers, drive innovations, and help deliver robust silicon across advanced nodes.

Qualifications

• 11+ years with BS in CS/Engineering, or 9+ with MS, or 7+ with PhD.
• 7+ years in full physical design flows: synthesis, P&R, CTS, timing, signoff.
• Top-level floorplanning for GPU/SoC; low-power design and DRC/LVS.
• Power-grid design/implementation using PNR tools; robustness analysis.
• Experience with STA, timing convergence and reliability considerations.
• Strong Python/Tcl/Shell/Perl scripting for automation.

Responsibilities

• Lead top-level floorplanning and power-grid implementation for GPU/SoC.
• Drive PPA targets with scalable flow innovations and methodology.
• Collaborate with architecture, RTL, software, and foundry teams.
• Mentor junior engineers and promote ownership and continuous learning.
• Develop or rewrite physical design flows for improved quality and productivity.

Skills

Physical design

Floorplanning

Power-grid design

Timing closure

Scripting/Automation

Team collaboration

Problem solving

Mentoring

Education

Bachelor's degree in CS/Engineering

MS or PhD (preferred)

Tools

FusionCompiler

Innovus

ICC2

PrimeTime/Tempus

StarRC

Job description

Samsung Austin Research and Development Center seeks a Senior Staff GPU Physical Design Engineer to shape full-chip and block-level implementation, focusing on top-level floorplanning, routing, and signoff for high-performance GPU IP. You will advance methodology, automate flows, and collaborate across architecture, RTL, and system teams.

With 11+ years in physical design or 7+ with a PhD, you will mentor engineers, drive innovations, and help deliver robust silicon across advanced nodes.