Senior GPU Physical Design Lead: Top‑Level Floorplanning

Samsung Semiconductor; Austin (TX); On-site; USD 180,200 - 270,400; Full time

Job summary

Samsung Austin Research and Development Center (SARC) seeks a Senior Staff GPU Physical Design Engineer to shape full-chip and block-level implementation, focusing on top-level floorplanning, placement, routing, CTS, and signoff for GPU/SoC designs.

Collaborate with architecture, RTL, and design technology teams to drive power optimization, reliability, and scalable flow across advanced nodes, mentoring engineers and advancing methodologies.

Qualifications

• 7+ years hands-on experience with full physical design flows (synthesis to signoff).
• Strong top-level floorplanning for GPU/SoC designs; low-power and DRC/LVS.
• Power-grid design experience using PNR tools (FusionCompiler, Innovus).
• Proficient in Python, Tcl, Shell, or Perl for automation.
• Experience with timing analysis and convergence methodologies (STA).
• Excellent collaboration and communication in a global team environment.

Responsibilities

• Lead top-level floorplanning, placement, routing, CTS, timing closure and signoff for GPU/SoC designs.
• Develop and optimize power-grid implementation to meet PPA targets.
• Drive methodology, automation, and scalable design practices across projects.
• Collaborate with architecture, RTL, advanced design technology, software and vendors to align design assumptions.
• Mentor junior engineers and foster a culture of ownership and continuous learning.

Skills

Physical design

Power-grid design

Floorplanning

Scripting

EDA tools

Timing closure

Mentoring

Collaboration

Education

Bachelor's degree in CS/Engineering

Master's degree

Ph.D.

Tools

FusionCompiler

Innovus

ICC2

Fusion Compiler/Innovus

PrimeTime/Tempus

StarRC

RedHawk

Job description

Samsung Austin Research and Development Center (SARC) seeks a Senior Staff GPU Physical Design Engineer to shape full-chip and block-level implementation, focusing on top-level floorplanning, placement, routing, CTS, and signoff for GPU/SoC designs.

Collaborate with architecture, RTL, and design technology teams to drive power optimization, reliability, and scalable flow across advanced nodes, mentoring engineers and advancing methodologies.