Senior GPU RTL Power Engineer - Power-Efficient GPU

Samsung Electronics Perú; Austin (TX); On-site; USD 124,000 - 186,000; Full time

Benefits offered by this job

Medical

Dental

Vision

Life insurance

401(k)

Onsite lunch

Employee purchase program

Tuition assistance

Paid time off

Wellness incentives

Job summary

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) is seeking a Senior GPU RTL Power Engineer to drive power optimization for mobile GPU IP blocks.

You will partner with hardware, software, and system teams to apply RTL-level and microarchitectural power strategies, exploring clock gating, voltage scaling, and low-power modes to deliver energy-efficient, high-performance designs.

Qualifications

• Experience in GPU/CPU architecture, microarchitecture and high-performance digital design with PPA tradeoffs.
• Familiarity with RTL power analysis and optimization tools.
• Proficiency in SystemVerilog and ASIC design flow (RTL, synthesis, timing, power).
• Knowledge of low-power techniques (clock gating, power gating, DVFS).

Responsibilities

• Contribute to power optimization for GPU blocks and subsystems.
• Collaborate with RTL, performance, modeling, and validation teams to apply power-saving techniques.
• Define power-aware design choices and tradeoffs balancing performance, power, and area.
• Document methodologies, results, and power optimization best practices.
• Stay ahead of GPU technologies and explore new power-saving techniques.

Skills

GPU/CPU architecture

RTL power analysis

SystemVerilog

Scripting (Python/Perl)

Power optimization

Collaboration

Debugging/data-driven

Timing analysis

Education

Bachelor's degree in CS/CE or MS

Tools

PowerArtist

PTPX

Empower

Job description

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) is seeking a Senior GPU RTL Power Engineer to drive power optimization for mobile GPU IP blocks.

You will partner with hardware, software, and system teams to apply RTL-level and microarchitectural power strategies, exploring clock gating, voltage scaling, and low-power modes to deliver energy-efficient, high-performance designs.