Senior Staff PPA Engineer – IC Physical Design Lead

Samsung Electronics Perú; Austin (TX); On-site; USD 180,000 - 270,000; Full time

Benefits offered by this job

Medical, dental, vision

401(k)

Onsite lunch

Tuition assistance

Job summary

Samsung Austin Research and Development Center (SARC/ACL) seeks a Sr Staff Physical Design PPA Engineer to drive PPA improvements for premium IP blocks. You will own flows from synthesis to place-and-route and ensure signoff meets aggressive targets.

Role requires deep PD implementation experience, strong problem-solving, scripting in TCL/Perl/Python, and collaboration with RTL and SOC teams to deliver high-quality, power-efficient designs.

Qualifications

• 10+ years of experience in physical design implementation or related field.
• Solid understanding of SOC/ASIC design flow and taping out designs.
• Experience with latest P&R/STA flows and tools; strong scripting skills.

Responsibilities

• Lead PPA initiatives by identifying opportunities and delivering solutions meeting project requirements.
• Drive flows and methodologies to automate Physical Design implementation.
• Collaborate with RTL and SOC teams to resolve design issues and optimize flows.
• Hands-on responsibility from synthesis to place-and-route through signoff, including timing and physical verification.
• Work on synthesis, floorplanning, place & route in chip-level and hierarchical environments to meet PPA targets.
• Interact with RTL counterparts and SOC teams to ensure design issues are addressed.
• Ensure work meets high quality standards for frequency, power, and area.

Skills

Synthesis

Place & route

PPA

Scripting

EDA tools

Communication

Problem solving

Education

Bachelor's degree in Computer Science/Computer Engineering or relevant field

Master's degree

PhD

Tools

Synthesis tools

P&R tools

CTS tooling

Job description

Samsung Austin Research and Development Center (SARC/ACL) seeks a Sr Staff Physical Design PPA Engineer to drive PPA improvements for premium IP blocks. You will own flows from synthesis to place-and-route and ensure signoff meets aggressive targets.

Role requires deep PD implementation experience, strong problem-solving, scripting in TCL/Perl/Python, and collaboration with RTL and SOC teams to deliver high-quality, power-efficient designs.