Senior STA Engineer — Timing Closure & Optimization

Quest Global; San Jose (CA); On-site; USD 160,000 - 220,000; Full time

Benefits offered by this job

401(k)

Dental insurance

Health insurance

Life insurance

Paid time off

Referral program

Vision insurance

Short/Long Term Disability

Job summary

Quest Global seeks an experienced STA/Timing Engineer to develop and validate timing constraints for complex SoC designs. You will work with Synopsys tools to perform synthesis, equivalency checking and STA, handling block and multi‑voltage timing closures.

You will define signoff methodologies, run QoR analyses, automate timing tasks with Tcl/Perl, and advise on clock tree synthesis for energy-efficient designs. This is an on-site role in California with strong collaboration across teams.

Qualifications

• Bachelor’s degree with 8+ years of related experience.
• Masters/PhD with relevant experience may be considered.

Responsibilities

• Develop and validate timing constraints for intricate SoC designs.
• Expertise in Synthesis, Equivalency Checking and STA.
• Must have Block Level and Multi-voltage Timing Closure experience. Top Level Timing Closure experience a plus.
• Experience with Synopsys Tools – DC/FC, Formality and PrimeTime for STA.
• Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
• Conduct pre-route timing checks and QoR analysis.
• Automate timing analysis processes using Tcl or Perl.
• Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
• Ensure compliance with timing signoff checklists and criteria.

Skills

Timing constraints

Synthesis

Equivalency Checking

STA

Clock tree planning

Tcl/Perl scripting

PrimeTime

ASIC design flows

Communication

Teamwork

Education

Bachelor's degree

Tools

Synopsys DC/FC

Synopsys Formality

PrimeTime

Genus

Job description

Quest Global seeks an experienced STA/Timing Engineer to develop and validate timing constraints for complex SoC designs. You will work with Synopsys tools to perform synthesis, equivalency checking and STA, handling block and multi‑voltage timing closures.

You will define signoff methodologies, run QoR analyses, automate timing tasks with Tcl/Perl, and advise on clock tree synthesis for energy-efficient designs. This is an on-site role in California with strong collaboration across teams.