Advanced-Node Static Timing & Signoff Engineer

Central Business Solutions, Inc; San Diego (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Central Business Solutions, Inc. is seeking a Static Timing Analysis (STA) engineer in San Diego, CA (preferred) to lead timing signoff on advanced-node designs.

You will own timing constraints, drive block- and full-chip closure across modes and corners, and collaborate with synthesis, P&R, and DFT teams to deliver silicon-ready timing signoff. The ideal candidate has strong STA fundamentals, hands-on PrimeTime/PrimeTime SI experience, and a track record closing timing on high-frequency designs

Qualifications

• Strong fundamentals in static timing analysis (setup/hold, slack, derating).
• Hands-on experience with PrimeTime/PrimeTime SI for signoff.
• Proficiency in developing and validating SDC constraints.
• MMM CMC analysis and closure experience.
• Knowledge of crosstalk/SI analysis and RC extraction.
• Scripting in TCL; Python or Perl for automation.
• Experience with advanced nodes (16nm/7nm/5nm/3nm FinFET).
• Excellent communication and cross-functional collaboration.

Responsibilities

• Develop, review, and maintain timing constraints and dependencies.
• Perform block-level and full-chip timing signoff across MMMC.
• Close setup/hold violations and generate timing ECOs.
• Run SI analysis and correlate with extraction and physical data.
• Validate RC corners and parasitic extraction.
• Apply variation-aware timing methods and signoff.
• Build timing abstracts and interface models for hierarchical designs.
• Automate timing analysis flows using TCL/Python.
• Collaborate with synthesis, P&R, CTS, DFT, and IR/EM teams.

Skills

Static timing analysis

PrimeTime

SDC constraints

MMM CMC analysis

OCV/AOCV/POCV

Crosstalk analysis

Parasitic extraction

SPEF

TCL scripting

Python

Debugging

Communication

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering (preferred)

Tools

Cadence Tempus

Quantus QRC

StarRC

PrimeTime

Job description

Central Business Solutions, Inc. is seeking a Static Timing Analysis (STA) engineer in San Diego, CA (preferred) to lead timing signoff on advanced-node designs.

You will own timing constraints, drive block- and full-chip closure across modes and corners, and collaborate with synthesis, P&R, and DFT teams to deliver silicon-ready timing signoff. The ideal candidate has strong STA fundamentals, hands-on PrimeTime/PrimeTime SI experience, and a track record closing timing on high-frequency designs