Senior STA Engineer

Quest Global; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Quest Global is seeking an STA engineer in San Jose, CA to lead timing closure across chip topologies. The role focuses on ensuring robust performance through full-chip and block-level analysis, with emphasis on timing budgets and signoff readiness.

You will debug timing issues, perform synthesis, equivalence checking and STA using Synopsys tools in a fast-paced environment supporting Fortune 500 clients.

Qualifications

• Experience with full-chip and block-level timing closure.
• Debug and fix timing issues across multiple corners.
• Proficient in synthesis, equivalence checking and STA.
• Strong understanding of timing constraints, CTS and clock constraints.
• Experience with Synopsys tools: DC/FC, Formality, PrimeTime.

Skills

Full Chip Timing Closure

Block Level Timing Closure

Multi-Voltage Timing Closure

Debug Timing Issues

Synthesis (DC/FC)

Equivalency Checking

STA (Static Timing Analysis)

Timing Constraints

CTS

MMM Timing Closure

Tools

Synopsys DC/FC

Synopsys Formality

Synopsys PrimeTime

Job description

Quest Global delivers world-class end-to-end engineering solutions by leveraging our deep industry knowledge and digital expertise. By bringing together technologies and industries, alongside the contributions of diverse individuals and their areas of expertise, we are able to solve problems better, faster. This multi-dimensional approach enables us to solve the most critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries.

We are looking for humble geniuses, who believe that engineering has the potential to make the impossible possible; innovators, who are not only inspired by technology and innovation, but also perpetually driven to design, develop, and test as a trusted partner for Fortune 500 customers. As a team of remarkably diverse engineers, we recognize that what we are really engineering is a brighter future for us all. If you want to contribute to meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you.

The achievers and courageous challenge-crushers we seek, have the following characteristics and skills:

• Must have Full Chip (Top Level) and Block Level and Multi-voltage Timing Closure experience.
• Debug and Fix Timing Issues
• This STA engineer needs to do Synthesis, Equivalency Checking and STA
• Good understanding of Timing Constraints, Exceptions, CTS and clock constraints, Multi-Mode Multi-Corner timing closure expertise.
• They use all Synopsys Tools – Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA