STA Engineer

Stellar IT Solutions; San Jose (CA); On-site; USD 140,000 - 220,000; Full time

Job summary

Stellar IT Solutions in San Jose/Austin seeks a Senior/Staff STA Engineer to own timing analysis and signoff for blocks and full‑chip SoCs on advanced nodes, using the Synopsys toolchain. You will set closure strategy and guide junior engineers.

Responsibilities include leading block‑level and full‑chip signoff in PrimeTime and PrimeTime‑SI, developing SDC constraints, running MCMM analyses, driving timing closure through ECOs, and collaborating with RTL, synthesis, PD and DFT teams to ensure

Qualifications

• 10+ years in STA and timing signoff
• Full-chip PrimeTime signoffs taken to tape-out
• Strong PT-SI, SDC authoring, SPEF/StarRC parasitic flows
• Timing ECO closure experience including crosstalk and noise fixes
• Deep-submicron experience (7nm or below preferred)
• TCL scripting proficiency

Responsibilities

• Lead block-level and full-chip STA signoff in PrimeTime (PT) and PrimeTime-SI.
• Develop and maintain SDC constraints, clocks, exceptions, and CDC/MCP/false-path handling.
• Run multi-corner, multi-mode (MCMM) analysis with OCV/AOCV/POCV derates.
• Drive timing closure through ECOs (PrimeTime ECO, Tweaker, ICC2/Fusion Compiler).
• Work with RTL, synthesis, physical design, DFT and clocking teams on closure strategy and milestones.
• Check timing at synthesis and handoff to PD.
• Build and improve STA flows and automation in TCL/Python.
• Mentor junior engineers and review their signoff.

Skills

Timing analysis

Signoff management

Mentoring

TCL scripting

Python scripting

Team collaboration

Clocking concepts

Education

BS in EE/ECE

MS in EE/ECE

Tools

PrimeTime

PrimeTime-SI

Fusion Compiler

Design Compiler

Job description

Senior/ Staff STA Engineer – Synopsys Flow (PrimeTime)

Location: Austin, TX/ San Jose, CA

Experience Required: 10+ years

Overview:

Own timing analysis and signoff closure for blocks, subsystems and full-chip SoCs on advanced nodes, using the Synopsys toolchain. At this level you will also set closure strategy and guide junior engineers.

Responsibilities:

• Lead block-level and full-chip STA signoff in PrimeTime (PT) and PrimeTime-SI.
• Develop and maintain SDC constraints, clocks, exceptions, and CDC/MCP/false-path handling.
• Run multi-corner, multi-mode (MCMM) analysis with OCV/AOCV/POCV derates.
• Drive timing closure through ECOs (PrimeTime ECO, Tweaker, ICC2/Fusion Compiler), covering setup, hold, crosstalk, noise and power.
• Work with RTL, synthesis, physical design, DFT and clocking teams on closure strategy and milestones.
• Check timing at synthesis (Design Compiler / Fusion Compiler) and at handoff to PD.
• Build and improve STA flows and automation in TCL/Python.
• Mentor junior engineers and review their signoff.

Must have:

• BS/MS in EE/ECE with 10+ years in STA and timing signoff.
• Several full-chip PrimeTime signoffs taken to tape-out.
• Strong PT-SI, SDC authoring, and SPEF/StarRC parasitic flows.
• Timing ECO closure experience, including crosstalk and noise fixes.
• Deep-submicron experience (7nm or below preferred).
• TCL scripting.

Nice to have:

• Design Compiler / Fusion Compiler and ICC2 exposure.
• Formality/equivalence checking.
• DFT timing closure (scan, BIST, MBIST).
• Python/Perl automation and flow ownership.
• Experience on networking, SoC, CPU or GPU silicon.