Synthesis & STA Engineer — Lead Timing Closure

I2Intech LLC; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

I2Intech LLC is seeking a Synthesis & STA Engineer to own timing constraints from RTL through post-route across corners and modes in San Jose, CA. You will develop constraints, run synthesis with Design Compiler/Genus and lead STA signoff for blocks and full-chip.

The role requires close collaboration with RTL, PD and DFT teams, hands-on experience with PrimeTime/Tempus, Formality/Conformal and at least two tape-outs, delivering predictable timing closure.

Qualifications

• Bachelor’s or Master’s in Electrical Engineering.
• Hands-on experience with synthesis and STA tools.
• Deep understanding of timing concepts: clocks, exceptions, CDC, derates and variation.
• Experience writing and debugging SDC constraints for complex SoCs.
• Experience with at least two tape-outs.

Responsibilities

• Develop and validate SDC constraints for functional and test modes.
• Run RTL-to-gate synthesis with Design Compiler/Genus and optimise PPA.
• Perform multi-corner, multi-mode STA using PrimeTime or Tempus.
• Analyse and fix timing violations; drive timing ECOs with PD.
• Run formal equivalence (Conformal/Formality) and constraint checks.
• Perform signoff timing including SI, OCV/AOCV/POCV and IR-aware analysis.

Skills

Synthesis

STA

Timing constraints

Signoff

PPA optimization

Scripting

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Tools

Design Compiler

Genus

PrimeTime

Tempus

Conformal/Formality

Job description

I2Intech LLC is seeking a Synthesis & STA Engineer to own timing constraints from RTL through post-route across corners and modes in San Jose, CA. You will develop constraints, run synthesis with Design Compiler/Genus and lead STA signoff for blocks and full-chip.

The role requires close collaboration with RTL, PD and DFT teams, hands-on experience with PrimeTime/Tempus, Formality/Conformal and at least two tape-outs, delivering predictable timing closure.