STA Design Engineer – Timing Signoff & Automation

NXP Semiconductors; Austin (TX); On-site; USD 120,000 - 165,000; Full time

Job summary

NXP Semiconductors in the United States is seeking an experienced ASIC Timing Analyst responsible for end-to-end timing signoff, constraints creation, and validation across frontend, IP, DFT teams to ensure timing closure for flagship SoCs. You will work with implementation owners and Full-Chip STA teams, generate timing fixes, and drive automation strategies to improve scalability and design quality.

Strong knowledge of Synopsys STA tools, scripting in Python/TCL, and experience with advanced

Qualifications

• Bachelor’s or Master’s in Electrical / Electronics Engineering or related field.
• Experience with ASIC/SoC timing analysis and STA tool flows.
• Strong communication skills.

Responsibilities

• End-to-End Constraints and Timing Signoff Ownership: Drive timing constraints creation and validation.
• Work with Frontend, IP and DFT teams to validate constraints and resolve timing issues.
• Provide timing feedback during all design stages and create automated/manual timing fixes.
• Support post-silicon bring-up, yield improvement, and production ramp activities.

Skills

STA and signoff methodologies

Timing ECO Generation

Constraints Development

Advanced node implementation

Python scripting

AI-driven scripting familiarity

Education

Bachelor’s or Master’s in Electrical / Electronics Engineering or related field

Tools

Synopsys flows

Job description

NXP Semiconductors in the United States is seeking an experienced ASIC Timing Analyst responsible for end-to-end timing signoff, constraints creation, and validation across frontend, IP, DFT teams to ensure timing closure for flagship SoCs. You will work with implementation owners and Full-Chip STA teams, generate timing fixes, and drive automation strategies to improve scalability and design quality.

Strong knowledge of Synopsys STA tools, scripting in Python/TCL, and experience with advanced