Senior STA Engineer — Timing Closure & Synthesis Expert

Quest Global; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

Quest Global is seeking an STA engineer in San Jose, CA to lead timing closure across chip topologies. The role focuses on ensuring robust performance through full-chip and block-level analysis, with emphasis on timing budgets and signoff readiness.

You will debug timing issues, perform synthesis, equivalence checking and STA using Synopsys tools in a fast-paced environment supporting Fortune 500 clients.

Qualifications

• Experience with full-chip and block-level timing closure.
• Debug and fix timing issues across multiple corners.
• Proficient in synthesis, equivalence checking and STA.
• Strong understanding of timing constraints, CTS and clock constraints.
• Experience with Synopsys tools: DC/FC, Formality, PrimeTime.

Skills

Full Chip Timing Closure

Block Level Timing Closure

Multi-Voltage Timing Closure

Debug Timing Issues

Synthesis (DC/FC)

Equivalency Checking

STA (Static Timing Analysis)

Timing Constraints

CTS

MMM Timing Closure

Tools

Synopsys DC/FC

Synopsys Formality

Synopsys PrimeTime

Job description

Quest Global is seeking an STA engineer in San Jose, CA to lead timing closure across chip topologies. The role focuses on ensuring robust performance through full-chip and block-level analysis, with emphasis on timing budgets and signoff readiness.

You will debug timing issues, perform synthesis, equivalence checking and STA using Synopsys tools in a fast-paced environment supporting Fortune 500 clients.