Lead STA & Synthesis Engineer for SoC Timing

Broadcom, Inc.; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Discretionary bonus

Equity awards

Job summary

Broadcom Inc. seeks a lead STA/Synthesis engineer to drive constraint development, validation, and timing closure for mission-critical IP and ASIC blocks in state-of-the-art technology nodes.

In this role, you will perform STA with PrimeTime/Tempus, lead synthesis and audits, and define robust signoff methodologies while optimizing clock trees for energy efficiency and performance. Collaboration across teams is essential.

Qualifications

• Experience with high-complexity silicon in advanced nodes.
• Familiarity with timing constraint development for hierarchical designs.
• Knowledge of clock tree planning and implementation for SoCs.
• Experience with timing ECO creation and final timing signoff.
• Proficiency in using STA tools (PrimeTime, TCM, Tempus) and scripting (Tcl, Perl).
• Proficiency in using synthesis and audit tools (DC-T, Genus, Fishtail, VCLP, Formality).
• Strong problem-solving skills and attention to detail.
• Effective communication and teamwork abilities.

Responsibilities

• Develop and validate timing constraints for intricate SoC designs.
• Perform static timing analysis (STA) using industry-standard tools (e.g., PrimeTime, Tempus)
• Perform synthesis and run static audits (CDC, RDC, Low Power, equivalence) for high speed, complex digital and mixed signal blocks
• Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.
• Conduct pre-route timing checks and quality of results (QoR) analysis.
• Automate timing analysis processes using scripting languages such as Tcl or Perl.
• Provide guidance on clock tree synthesis and optimization for energy-efficient designs.
• Ensure compliance with timing signoff checklists and criteria.
• Generate timing ECO's for timing closure
• Drive timing closure for complex IP and ASIC blocks

Skills

Static Timing Analysis

Scripting (Tcl/Perl)

Cross-functional teamwork

Problem solving

Independent work

Communication skills

Education

Bachelor's degree

Master's degree

PhD

Tools

PrimeTime

Tempus

DC-T

Genus

Formality

VCLP

Fishtail

Job description

Broadcom Inc. seeks a lead STA/Synthesis engineer to drive constraint development, validation, and timing closure for mission-critical IP and ASIC blocks in state-of-the-art technology nodes.

In this role, you will perform STA with PrimeTime/Tempus, lead synthesis and audits, and define robust signoff methodologies while optimizing clock trees for energy efficiency and performance. Collaboration across teams is essential.