Senior SoC Video Verification Engineer - Multimedia Lab

TikTok; San Jose (CA); On-site; USD 213,000 - 450,000; Full time

Job summary

TikTok is seeking a video codec verification engineer to design and verify ASIC/SoC accelerators for video encoding. You will build reusable UVM environments, drive coverage, and participate in GLS timing simulation while collaborating with teams across hardware and software.

The role requires 3+ years in ASIC/SoC verification, strong SystemVerilog/UVM expertise, and proficiency with VCS/Incisive/Questa and Verdi. On-site in the San Jose area, with healthcare and full-time benefits.

Qualifications

• Bachelor's degree or higher in Microelectronics, Computer Science, Electronic Communications, or a related field.
• 3+ years of working experience in ASIC/SoC verification.
• Mastery of SystemVerilog and UVM methodology, with the ability to independently build IP-level or SoC-level verification environments.
• Proficiency in mainstream simulation and debugging tools (VCS/Incisive/Questa, Verdi, etc.).
• Exceptional debugging and logical analysis skills; proficient in Python/Perl/Shell scripting for automation.

Responsibilities

• Verification Planning: analyze architecture and design specs to develop high-coverage module/SoC test plans.
• Environment Development: build or maintain advanced verification environments (Testbench) using UVM.
• Test Execution & Closure: develop test cases, run constrained random and directed tests, drive 100% coverage.
• System-Level Verification: gate-level simulation, GLS, and timing simulation; assist in FPGA prototyping and co-debugging.
• Flow Optimization: maintain regression scripts and automation to improve verification efficiency.

Skills

SystemVerilog

UVM methodology

ASIC/SoC verification

VCS/Incisive/Questa

Python/Perl/Shell scripting

Debugging & analysis

Education

Bachelor's degree or higher in Microelectronics/CS/EC or related

Tools

VCS/Incisive/Questa

Verdi

Job description

TikTok is seeking a video codec verification engineer to design and verify ASIC/SoC accelerators for video encoding. You will build reusable UVM environments, drive coverage, and participate in GLS timing simulation while collaborating with teams across hardware and software.

The role requires 3+ years in ASIC/SoC verification, strong SystemVerilog/UVM expertise, and proficiency with VCS/Incisive/Questa and Verdi. On-site in the San Jose area, with healthcare and full-time benefits.