Senior SoC Digital Design Engineer - Video Codec Hardware

TikTok; San Jose (CA); On-site; USD 213,000 - 450,000; Full time

Benefits offered by this job

Health insurance

401(k) plan

Paid parental leave

Disability insurance

Life insurance

Wellbeing benefits

Paid holidays

Paid sick days

Paid personal time

Job summary

TikTok is seeking a video codec hardware design engineer in San Jose, CA to architect and implement SoC topologies and subsystems. You will develop RTL in Verilog/SystemVerilog and work with verification, synthesis, and power teams to optimize performance and area.

The role requires strong RTL/VLSI fundamentals, experience with EDA tools, and scripting for automation. Join a fast-growing hardware team delivering scalable video platforms.

Qualifications

• Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field.
• 3+ years of experience in digital front-end design (open to highly promising candidates with less experience).
• Mastery of Verilog/SystemVerilog and a solid foundation in digital circuits.
• Proficiency with mainstream front-end EDA tools (e.g., Spyglass, Design Compiler, PrimeTime).
• Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for workflow automation.

Responsibilities

• Architecture Design: Define the architecture of SoC top or subsystems and evaluate power, performance, and area in early design.
• RTL Implementation: Write high-quality RTL code (Verilog/SystemVerilog) and maintain design docs.
• Front-End Quality Control: Perform Lint, CDC, and RDC checks to ensure standard compliance.
• Cross-Functional Collaboration: Work with Verification for debugging and with Backend/Mid-end teams for synthesis and timing.
• Low Power Design: Formulate chip low-power strategies, apply Clock Gating and Power Gating, support UPF flow.

Skills

Digital front-end design

Verilog/SystemVerilog

Scripting (Python/Perl/Tcl)

RTL design

Education

Bachelor's degree or higher in Microelectronics / ICs / EE

Tools

Spyglass

Design Compiler

PrimeTime

Job description

TikTok is seeking a video codec hardware design engineer in San Jose, CA to architect and implement SoC topologies and subsystems. You will develop RTL in Verilog/SystemVerilog and work with verification, synthesis, and power teams to optimize performance and area.

The role requires strong RTL/VLSI fundamentals, experience with EDA tools, and scripting for automation. Join a fast-growing hardware team delivering scalable video platforms.