Senior Silicon DV Engineer — Video Codec & HLS

Google Inc.; Mountain View (CA); On-site; USD 142,000 - 236,000; Full time

Job summary

Google Mountain View seeks a Senior Silicon Design Verification Engineer for YouTube Video Accelerators to own verification across C/C++ and RTL, bridging algorithmic intent with hardware implementation. You will lead HLS verification workflows, develop advanced testbenches, and collaborate with design teams to ensure high-quality silicon for video workflows.

The role emphasizes ownership of verification life-cycle, from planning to coverage closure, with expertise in SystemVerilog/UVM, C/C++,

Qualifications

• Bachelor's degree or equivalent practical experience.
• 8 years of design verification experience.
• Experience with SystemVerilog and UVM.

Responsibilities

• Lead comprehensive verification strategies and signoff for complex blocks from C/C++ to RTL.
• Develop and maintain environments using C/C++ GoogleTest for functional validation and SystemVerilog/UVM for RTL timing and interactions.
• Use HLS methods such as C/RTL co-simulation and formal equivalence verification to ensure hardware fidelity.
• Drive bug hunting and coverage analysis across C++ and RTL domains to ensure complete verification.
• Mentor junior engineers on HLS verification and optimize C++ code for verifiability.

Skills

SystemVerilog

UVM

Design verification

C/C++

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical/Computer Engineering or Computer Science (preferred)

Tools

VCS

Xcelium

Verdi

Job description

Google Mountain View seeks a Senior Silicon Design Verification Engineer for YouTube Video Accelerators to own verification across C/C++ and RTL, bridging algorithmic intent with hardware implementation. You will lead HLS verification workflows, develop advanced testbenches, and collaborate with design teams to ensure high-quality silicon for video workflows.

The role emphasizes ownership of verification life-cycle, from planning to coverage closure, with expertise in SystemVerilog/UVM, C/C++,