Senior SoC Physical Design Architect — 5nm Tapeout

RiseMe; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

NXP is seeking an experienced Digital Designer for SoC Implementation / Physical Design to own end-to-end physical design execution from RTL to silicon for advanced nodes. The role requires deep technical expertise to deliver optimized PPA while meeting silicon milestones.

The ideal candidate will lead a team, mentor engineers, coordinate with architecture, RTL, verification, and product teams, and drive method development and automation for next-generation designs.

Qualifications

• Bachelor’s or Master’s in Electrical Engineering or related field.
• 10+ years ASIC/SoC physical design experience.
• Strong knowledge of industry EDA tools (Synopsys, Cadence) and flow.

Responsibilities

• Own end-to-end physical design from RTL to GDSII, including floorplanning, synthesis, place & route, CTS, routing, STA, PDN, PDV and signoff.
• Drive timing, power, IR/EM, and physical verification closure to tapeout readiness.
• Deliver optimized PPA across complex designs and improve design quality.

Skills

Team Leadership

Mentoring

Communication

Education

Bachelor’s or Master’s in Electrical Engineering or related field

Tools

Synopsys

Cadence

Job description

NXP is seeking an experienced Digital Designer for SoC Implementation / Physical Design to own end-to-end physical design execution from RTL to silicon for advanced nodes. The role requires deep technical expertise to deliver optimized PPA while meeting silicon milestones.

The ideal candidate will lead a team, mentor engineers, coordinate with architecture, RTL, verification, and product teams, and drive method development and automation for next-generation designs.