Principal Physical Design Engineer / Physical Design – ACE US

NXP Semiconductors; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

NXP Semiconductors seeks an experienced Digital Designer for SoC Implementation / Physical Design to own end-to-end PD execution from RTL to silicon, targeting advanced nodes with optimized PPA. You will drive floorplanning, synthesis, place & route, CTS, routing, STA and signoff while collaborating with architecture, RTL, verification and product teams.

Ideal candidates bring 10+ years of ASIC/SoC PD experience, strong knowledge of Synopsys/Cadence flows, and scripting in Python, TCL and Perl.

Qualifications

• Bachelor’s or Master’s in Electrical / Electronics Engineering or related field.
• 10+ years of experience in ASIC/SoC physical design.
• Strong knowledge of industry EDA tools (Synopsys, Cadence).

Responsibilities

• End-to-End Physical Design Ownership: Lead Physical design execution including floorplanning, synthesis, place & route, CTS, routing, STA, PDN, PDV and signoff. Drive timing, power, IR/EM, and physical verification closure to achieve tapeout readiness.
• Team Leadership & Organization Development: Mentor and develop engineers, model execution discipline, review mechanisms, and performance tracking.
• Technical Strategy & Innovation: Define next-generation PD methodologies, drive automation and tool flow optimization, and adopt advanced nodes (5nm and beyond).
• Cross-Functional & Ecosystem Engagement: Collaborate with architecture, RTL, verification and product teams; engage with EDA vendors and IP providers; support post-silicon activities.

Skills

Strong communication skills

Leadership

ASIC/SoC PD experience

Education

Bachelor’s or Master’s in Electrical / Electronics Engineering or related field

Tools

Cadence flows

Synopsys flows

Python scripting

TCL scripting

Perl scripting

Job description

Role Summary

We are seeking an experienced Digital Designer for SoC Implementation / Physical Design for advanced semiconductor products. This role will own end-to-end physical design execution across complex designs, driving delivery from RTL to silicon for cutting-edge technology nodes. The ideal candidate demonstrates deep technical expertise to implement a given design on silicon with optimized quality and meeting PPA targets.

Key Responsibilities

• End-to-End Physical Design Ownership: Lead Physical design execution including floorplanning, synthesis, place & route, CTS, routing, STA, PDN, PDV and signoff. Drive timing, power, IR/EM, and physical verification closure to achieve tapeout readiness. Deliver optimized PPA (Power, Performance, Area) across complex designs. Aligns with internal expectations of implementing designs on silicon with optimal quality, PPA, and cost efficiency.
• Team Leadership & Organization Development: Participate in mentoring and career development. Role-Model execution discipline, review mechanisms, and performance tracking. Interface with senior leadership for status reporting, escalation, and decision-making.
• Technical Strategy & Innovation: Define and deploy next-generation physical design methodologies. Drive automation, flow optimization, and tool innovation. Lead adoption of advanced node technologies (5nm and beyond). Improve scalability, productivity, and design quality through methodology enhancements.
• Cross-Functional & Ecosystem Engagement: Collaborate with architecture, RTL, verification, and product teams to ensure design convergence. Interface with EDA vendors and IP providers for tool and flow optimization. Support post-silicon bring-up, yield improvement, and production ramp activities.

Core Technical Expertise

• Full RTL-to-GDSII implementation flow (Cadence and/or Synopsys tool sets)
• Floorplanning, synthesis, PNR, CTS, routing, STA and signoff methodologies
• Physical verification (DRC/LVS/ERC)
• Advanced node implementation (≤ 16nm / 5nm)
• Low power design (UPF/CLP)
• Scripting in Python, TCL, and Perl

Required Qualifications

• Bachelor’s or Master’s in Electrical / Electronics Engineering or related field
• 10+ years of experience in ASIC / SoC physical design
• Strong knowledge of industry EDA tools (Synopsys, Cadence flows)
• Strong communication skills

Preferred Qualifications

• Experience in high-reliability SoCs
• Exposure to AI-driven design methodologies and automation

Why This Role Matters

• Own delivery of flagship SoCs at advanced nodes
• Drive innovation in physical design methodologies
• Direct impact on silicon success and product competitiveness

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.

NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.com.

Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills. Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality. Thank you for considering a career at NXP.

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