Lead SoC Physical Design Engineer - 5nm

NXP Semiconductors; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

NXP Semiconductors seeks an experienced Digital Designer for SoC Implementation / Physical Design to own end-to-end PD execution from RTL to silicon, targeting advanced nodes with optimized PPA. You will drive floorplanning, synthesis, place & route, CTS, routing, STA and signoff while collaborating with architecture, RTL, verification and product teams.

Ideal candidates bring 10+ years of ASIC/SoC PD experience, strong knowledge of Synopsys/Cadence flows, and scripting in Python, TCL and Perl.

Qualifications

• Bachelor’s or Master’s in Electrical / Electronics Engineering or related field.
• 10+ years of experience in ASIC/SoC physical design.
• Strong knowledge of industry EDA tools (Synopsys, Cadence).

Responsibilities

• End-to-End Physical Design Ownership: Lead Physical design execution including floorplanning, synthesis, place & route, CTS, routing, STA, PDN, PDV and signoff. Drive timing, power, IR/EM, and physical verification closure to achieve tapeout readiness.
• Team Leadership & Organization Development: Mentor and develop engineers, model execution discipline, review mechanisms, and performance tracking.
• Technical Strategy & Innovation: Define next-generation PD methodologies, drive automation and tool flow optimization, and adopt advanced nodes (5nm and beyond).
• Cross-Functional & Ecosystem Engagement: Collaborate with architecture, RTL, verification and product teams; engage with EDA vendors and IP providers; support post-silicon activities.

Skills

Strong communication skills

Leadership

ASIC/SoC PD experience

Education

Bachelor’s or Master’s in Electrical / Electronics Engineering or related field

Tools

Cadence flows

Synopsys flows

Python scripting

TCL scripting

Perl scripting

Job description

NXP Semiconductors seeks an experienced Digital Designer for SoC Implementation / Physical Design to own end-to-end PD execution from RTL to silicon, targeting advanced nodes with optimized PPA. You will drive floorplanning, synthesis, place & route, CTS, routing, STA and signoff while collaborating with architecture, RTL, verification and product teams.

Ideal candidates bring 10+ years of ASIC/SoC PD experience, strong knowledge of Synopsys/Cadence flows, and scripting in Python, TCL and Perl.