Lead Physical Design Engineer - SoC & Tapeout Specialist

Celero Communications; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communication Inc. seeks an experienced Physical Design Engineer to lead the physical implementation of SoCs, overseeing floorplanning, power planning, place-and-route, CTS, timing closure, and physical verification.

You will collaborate with architecture, RTL, circuit design, and verification teams to ensure high-performance, manufacturable silicon ready for tapeout. The role calls for 5+ years in ASIC physical design, hands-on experience with 7nm/5nm/3nm flows, and mastery of Cadence

Qualifications

• 5+ years of ASIC physical design experience, with tapeout in advanced nodes.
• Proven ability to drive floorplanning, CTS, power planning, and routing for high-performance chips.
• Experience resolving STA, DRC, LVS issues and signoff requirements.
• Deep knowledge of EM/IR and physically aware synthesis techniques.
• Experience mentoring engineers and defining design methodologies.

Responsibilities

• RTL-to-GDSII execution for SoCs or complex digital blocks.
• Design optimization including floorplanning, power grid, and CTS for performance.
• Convergence of timing and signal integrity with frontend teams.
• Run STA and physical verification; fix DRC/LVS violations.
• Develop automation and robust flow improvements via scripting.
• Partner with architecture, RTL, and analog teams for tapeout readiness.

Skills

ASIC physical design

Floorplanning

P&R (Place & Route)

Timing closure

Cross-functional leadership

Scripting (Python/Tcl/Perl)

Tools

Cadence Innovus

Cadence Tempus

Cadence Voltus

Cadence Pegasus

Cadence Calibre

Job description

Celero Communication Inc. seeks an experienced Physical Design Engineer to lead the physical implementation of SoCs, overseeing floorplanning, power planning, place-and-route, CTS, timing closure, and physical verification.

You will collaborate with architecture, RTL, circuit design, and verification teams to ensure high-performance, manufacturable silicon ready for tapeout. The role calls for 5+ years in ASIC physical design, hands-on experience with 7nm/5nm/3nm flows, and mastery of Cadence