Senior SoC Physical Design Engineer - Tapeout & PPA

Micron Memory Malaysia Sdn Bhd; Folsom (CA); On-site; USD 177,000 - 334,000; Full time

Job summary

Micron Technology in Folsom, CA is looking for a senior SoC Physical Design Engineer to drive implementation from netlist to GDSII for advanced memory/SoC blocks. You will work with RTL, verification, DFT, IP, packaging and manufacturing to ensure top‑level integration with strong PPA and robust signoff.

The role demands hands‑on execution, ownership of blocks or top‑level integration, and strong scripting skills. A track record of tapeouts on leading foundries like TSMC is highly valued.

Qualifications

• Strong experience in SoC physical design implementation from netlist to GDSII.
• Proficiency with Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre.
• Experience with UPF/CPF power delivery concepts.
• Exposure to hierarchical physical design and large-scale integration.
• Tapeout history on advanced foundries (e.g., TSMC).
• Strong scripting skills using Python, TCL, Perl, and shell.

Responsibilities

• Own physical implementation for SoC blocks and/or top-level, including floor planning, placement, CTS, routing, and physical optimization to meet PPA targets.
• Drive timing closure (setup/hold) across MMMC scenarios; partner with RTL, architecture, and STA/signoff to converge designs.
• Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements.
• Integrate and implement complex IP with focus on robust physical integration and timing/power integrity.
• Perform and coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff.
• Work with packaging, assembly, test, probe, and manufacturing stakeholders to ensure design meets manufacturability and quality requirements.
• Support tapeout execution (checklists, ECO flows, signoff reviews) and contribute to post-silicon debug by correlating silicon behavior with PD/STA/power analysis.
• Identify flow gaps and improve productivity through scripting/automation and best-practice methodology development.

Skills

SoC physical design

Netlist to GDSII

Power intent / UPF

Hierarchy design

Scripting (Python/TCL)

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

Cadence Innovus/Tempus

Synopsys ICC2/PrimeTime

Siemens Calibre

Job description

Micron Technology in Folsom, CA is looking for a senior SoC Physical Design Engineer to drive implementation from netlist to GDSII for advanced memory/SoC blocks. You will work with RTL, verification, DFT, IP, packaging and manufacturing to ensure top‑level integration with strong PPA and robust signoff.

The role demands hands‑on execution, ownership of blocks or top‑level integration, and strong scripting skills. A track record of tapeouts on leading foundries like TSMC is highly valued.