Senior SoC DFT Engineer for HBM AI Systems

Micron Technology, Inc.; Folsom (CA); Sur place; USD 199 000 - 347 000; Plein temps

Résumé du poste

Micron Technology, Inc. in California is seeking a seasoned MTS SoC DFT Engineer for HBM. You will own DFT designs enabling manufacturability and silicon bring-up for advanced HBMs across multiple generations, partnering with RTL, synthesis, and physical design teams.

The role requires 10+ years in SoC/DFT, extensive experience with scan, MBIST/LBIST, JTAG, ATPG, and hands-on use of industry EDA tools. Relocation may be considered. Competitive base pay offered.

Qualifications

• Strong hands-on experience with SoC develop for test (DFT) architecture and implementation, including scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG.
• Experience across full RTL-to-GDS SoC flows and collaboration with synthesis, STA, and physical design teams.
• Proficiency with industry-standard EDA tools from Siemens, Synopsys, and Cadence for DFT and implementation.
• Bachelor's degree in Electrical/Computer Engineering or related field; 10+ years in SoC design/DFT/implementation.
• Experience with large, complex SoCs integrating multiple IP blocks and subsystems.

Responsabilités

• Own SoC-level DFT structures and their implementation, including scan, MBIST/LBIST, JTAG, and test access architectures for HBM base-die builds.
• Define and drive DFT architecture early in the design cycle, aligning with SoC integration, floorplanning, timing, power, and physical design requirements.
• Implement and integrate DFT logic at block, subsystem, and full-chip levels with RTL and SoC integration teams.
• Complete and sign off DFT flows, including linting, CDC checks, DFT rule checks, ATPG readiness, and coverage closure.
• Collaborate with physical design teams to optimize DFT for placement, routing, timing, and DRC/LVS signoff.
• Work with verification, product engineering, test, probe, and manufacturing to ensure testability, diagnosability, and pre/post-silicon bring-up.
• Mentor engineers, drive cross-group reviews, and explore Gen-AI/Agentic-AI solutions to improve DFT workflows.

Connaissances

SoC DFT architecture

ATPG/MBIST/LBIST

RTL-to-GDS flow

JTAG boundary scan

Python scripting

Formation

Bachelor's degree in Electrical or Computer Engineering or related field

Outils

Siemens

Synopsys

Cadence

Description du poste

Micron Technology, Inc. in California is seeking a seasoned MTS SoC DFT Engineer for HBM. You will own DFT designs enabling manufacturability and silicon bring-up for advanced HBMs across multiple generations, partnering with RTL, synthesis, and physical design teams.

The role requires 10+ years in SoC/DFT, extensive experience with scan, MBIST/LBIST, JTAG, ATPG, and hands-on use of industry EDA tools. Relocation may be considered. Competitive base pay offered.