Staff SoC DFT Engineer, HBM

Micron Technology, Inc; Richardson (TX); On-site; USD 130,000 - 160,000; Full time

Job summary

Micron Technology, Inc based in Richardson, Texas is seeking a Staff SoC DFT Engineer. This role involves owning SoC-level design for test architecture, including MBIST and JTAG, and executing DFT flows. The ideal candidate has strong hands-on DFT experience and a Bachelor's degree in Electrical Engineering.

The position requires collaboration with physical design teams and verification efforts, along with proficiency in industry-standard EDA tools. Micron seeks a passionate engineer for this innovative team.

Qualifications

• Strong hands-on experience with DFT architecture and implementation.
• Experience working across full RTL-to-GDS SoC flows.
• Seven or more years of relevant experience in SoC design.

Responsibilities

• Own SoC-level design for test architecture and implementation.
• Define and drive DFT architecture early in the design cycle.
• Execute and sign off DFT flows and checks.

Skills

SoC design for test (DFT) architecture

scan insertion

MBIST/LBIST concepts

JTAG

scripting languages (Python, Tcl, Perl)

Education

Bachelor’s degree in Electrical Engineering or related field

Tools

EDA tools from Siemens, Synopsys, Cadence

Job description

Req ID: JR102415 Staff SoC DFT Engineer, HBM

Job Profile(s): Systems Design Engineer 4

Relocation Level: TBD

Responsibilities

• Own SoC‑level design for test (DFT) architecture and implementation, including scan, memory built‑in self‑test (MBIST), logic built‑in self‑test (LBIST) where applicable, boundary scan (Joint Test Action Group, JTAG), and test access architectures for HBM base‑die designs.
• Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements.
• Implement and integrate DFT logic at block, subsystem, and full‑chip levels while partnering closely with register‑transfer level (RTL) design and SoC integration teams.
• Execute and sign off DFT flows, including linting, clock‑domain crossing (CDC) checks, DFT rule checks, automatic test pattern generation (ATPG) readiness, and coverage closure.
• Collaborate with physical design teams to optimize DFT solutions for placement, routing, timing closure, and design rule check/layout versus schematic (DRC/LVS) signoff.
• Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, smooth pre‑silicon debug, and post‑silicon bring‑up.
• Partner with computer‑aided design (CAD) and methodology teams to standardize and improve DFT flows, contribute to cross‑group technical reviews, mentor engineers as appropriate, and drive innovation for future HBM generations.

Minimum Qualifications

• Strong hands‑on experience with SoC design for test (DFT) architecture and implementation, including scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG.
• Experience working across full RTL‑to‑GDS SoC flows and collaborating with synthesis, static timing analysis (STA), and physical design teams.
• Proficiency using industry‑standard electronic design automation (EDA) tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• Seven or more years of relevant experience in SoC design, DFT, or implementation for complex digital application‑specific integrated circuits (ASICs) or SoCs.

Preferred Qualifications

• Experience with large, complex SoCs that integrate multiple intellectual property (IP) blocks and subsystems.
• Strong RTL debugging, design analysis, and problem‑solving skills.
• Experience using scripting languages such as Python, Tcl, or Perl for flow automation.
• Ability to communicate clearly and collaborate effectively across global, cross‑functional teams.
• Familiarity with memory systems such as dynamic random‑access memory (DRAM), high‑bandwidth memory (HBM), and related JEDEC specifications.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.