Senior SoC DFT Engineer – HBM/RTL-to-GDS Expert

Micron Memory Malaysia Sdn Bhd; Richardson (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Micron Technology in Richardson, TX is seeking a Staff SoC DFT Engineer to own design-for-test architecture for high-bandwidth memory base-die designs. You will drive DFT across RTL-to-GDS flows, implementing scan, MBIST/LBIST, JTAG, and ATPG readiness, collaborating with RTL, CAD, and physical design teams.

This role partners with verification, test, and manufacturing to ensure pre-silicon debug and post-silicon bring-up, mentors engineers, and helps advance future HBM generations.

Qualifications

• Strong hands‑on experience with SoC design for test (DFT) architecture and implementation, including scan insertion, MBIST/LBIST, boundary scan (JTAG), and ATPG.
• Experience across RTL-to-GDS flows with synthesis, STA, and physical design collaboration.
• Proficiency with industry‑standard EDA tools from Siemens, Synopsys, and Cadence for DFT and implementation.

Responsibilities

• Own SoC‑level DFT architecture and implementation across levels (block, subsystem, full chip).
• Define DFT architecture early in design cycles aligned with SoC integration, floorplanning, timing, power, and physical design.
• Collaborate with RTL, CAD, verification, test, and manufacturing teams to enable testability and post‑silicon bring‑up.

Skills

SoC DFT architecture

MBIST/LBIST concepts

JTAG boundary scan

ATPG

RTL-to-GDS flows

Scripting (Python/Tcl/Perl)

Memory systems (HBM/DRAM)

Cross-functional collaboration

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

Siemens

Synopsys

Cadence

Job description

Micron Technology in Richardson, TX is seeking a Staff SoC DFT Engineer to own design-for-test architecture for high-bandwidth memory base-die designs. You will drive DFT across RTL-to-GDS flows, implementing scan, MBIST/LBIST, JTAG, and ATPG readiness, collaborating with RTL, CAD, and physical design teams.

This role partners with verification, test, and manufacturing to ensure pre-silicon debug and post-silicon bring-up, mentors engineers, and helps advance future HBM generations.