HBM SoC DFT Engineer — High-Performance Testing

1000 Micron Technology, Inc.; Richardson (TX); On-site; USD 199,000 - 347,000; Full time

Benefits offered by this job

Health benefits

Bonus eligibility

Equity

Job summary

Micron Technology, Inc. is seeking a senior professional to lead design for test (DFT) for high‑bandwidth memory SoCs. You will own DFT architectures, implement scan, MBIST/LBIST, and JTAG, and drive testability across RTL to GDS flows.

Collaboration across RTL, synthesis, STA, and physical teams is essential for robust silicon bring‑up. Join a team advancing HBM technologies and AI workloads, with responsibility from early architecture to post‑silicon validation.

Qualifications

• Strong hands-on experience with SoC develop for test (DFT) architecture and implementation, including scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG.
• Experience across RTL‑to‑GDS SoC flows with synthesis, STA, and physical design collaboration.
• Bachelor’s degree in Electrical/Computer Engineering or equivalent practical experience.

Responsibilities

• Own SoC-level DFT structures and implementation, including scan, MBIST, LBIST, JTAG, and test access for HBM base‑die builds.
• Define and drive DFT architecture early in the design cycle, aligned with SoC integration, floorplanning, timing, power, and physical design requirements.
• Implement and integrate DFT logic at block, subsystem, and full‑chip levels with RTL design and SoC teams.
• Complete and sign off DFT flows, including linting, CDC checks, ATPG readiness, and coverage closure.
• Collaborate with physical design teams to optimize DFT for placement, routing, timing, and DRC/LVS signoff.
• Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability and post‑silicon bring‑up.
• Mentor engineers, drive cross‑group reviews, and push innovation for future HBM generations.
• Apply Gen‑AI and Agentic‑AI to improve DFT workflows and methodologies.

Skills

SoC DFT design

ATPG

MBIST/LBIST

JTAG

RTL-to-GDS

Synthesis/STA/Physical

Education

Bachelor’s degree in Electrical or Computer Engineering

Tools

Siemens

Synopsys

Cadence

Job description

Micron Technology, Inc. is seeking a senior professional to lead design for test (DFT) for high‑bandwidth memory SoCs. You will own DFT architectures, implement scan, MBIST/LBIST, and JTAG, and drive testability across RTL to GDS flows.

Collaboration across RTL, synthesis, STA, and physical teams is essential for robust silicon bring‑up. Join a team advancing HBM technologies and AI workloads, with responsibility from early architecture to post‑silicon validation.