Senior SoC DFT Engineer for HBM & TSV

Micron Technology, Inc.; Richardson, Northern (TX, KY); Hybrid; USD 199,000 - 347,000; Full time

Benefits offered by this job

Medical benefits

Dental and vision plans

Paid time off

Job summary

Micron Technology, Inc. seeks an experienced SoC DFT architect to own design-for-test hardware and verify testability across the RTL-to-GDS flow.

You will implement scan, MBIST/LBIST, JTAG, and ATPG concepts while coordinating with RTL, synthesis, STA, and physical design teams. This role emphasizes collaboration with CAD and verification to enable smooth pre-silicon debug and post-silicon bring-up.

Qualifications

• Extensive experience in SoC test architecture and DFT implementation including scan, MBIST/LBIST, JTAG, ATPG.
• Experience across RTL-to-GDS flows with synthesis, STA, and physical design teams.
• Proficient with industry-standard EDA tools from Siemens, Synopsys, Cadence.
• Bachelor's degree in Electrical/Computer Engineering; 10+ years in SoC DFT.

Responsibilities

• Own design-for-test (DFT) structures for SoC at the die and block levels.
• Define DFT architecture early in the design cycle and align with RTL and physical design teams.
• Implement and integrate DFT logic across RTL-to-GDS flows and signoff all DFT checks.
• Collaborate with CAD/verification/Manufacturing teams to ensure testability and pre/post-silicon bring-up.
• Apply Gen-AI/Agentic-AI approaches to improve DFT workflows.

Skills

SoC DFT

ATPG

MBIST/LBIST

RTL-to-GDS

Education

Bachelors in EE/CE

Tools

EDA tools

Job description

Micron Technology, Inc. seeks an experienced SoC DFT architect to own design-for-test hardware and verify testability across the RTL-to-GDS flow.

You will implement scan, MBIST/LBIST, JTAG, and ATPG concepts while coordinating with RTL, synthesis, STA, and physical design teams. This role emphasizes collaboration with CAD and verification to enable smooth pre-silicon debug and post-silicon bring-up.