Senior SoC Architect & Design Lead

Synopsys, Inc.; Sunnyvale (CA); Hybrid; USD 260,000 - 380,000; Full time

Job summary

Synopsys, Inc. in Sunnyvale, CA seeks a senior architect to lead design teams through full ASIC/FPGA cycles, from specification to GDSII handoff.

You will partition complex SOCs, balance performance and power, and drive RTL using SystemVerilog while collaborating with verification, DFT, and physical design groups. You will implement PCIe, Ethernet, and UCIe in SOC designs, refine design flows, and work with customers across aerospace, automotive, and HPC markets.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Engineering required.
• 15+ years of hands-on experience designing and verifying ASIC or FPGA devices through multiple tape-outs or production releases.
• Proven experience leading design teams, including mentoring engineers and managing technical execution across milestones.
• Deep understanding of the full ASIC design flow from micro-architecture through RTL development, synthesis, timing closure, and physical handoff.
• Strong SystemVerilog RTL coding skills with ability to design and review complex control and datapath logic.
• Working knowledge of PCIe, Ethernet, or UCIe in real production designs.
• Experience with ASIC development tools including simulators, lint tools, CDC/RDC checkers, synthesis tools, and static timing analysis platforms.

Responsibilities

• Lead design teams of junior and senior engineers through full ASIC and FPGA development cycles, from specification to GDSII handoff.
• Partition and architect complex SOC designs from customer requirements, creating high-level and micro-architectures that balance performance, area, and power.
• Drive RTL development using SystemVerilog, ensuring designs meet quality standards through code reviews, lint checks, CDC/RDC analysis, and synthesis readiness.
• Collaborate directly with verification, DFT, and physical design teams to resolve integration issues, timing closure challenges, and design-for-test requirements.
• Implement complex industry-standard protocols including PCIe, Ethernet, and UCIe within customer-specific SOC designs.
• Develop and refine ASIC design flows and methodologies using Synopsys and vendor tools for simulation, synthesis, static timing analysis, and signoff.
• Work hands-on with customers ranging from startups to industry leaders across automotive, aerospace, defense, and high-performance computing markets.

Skills

Leadership experience

SystemVerilog

RTL design

Timing closure

Synthesis

Verification collaboration

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

Simulators

Lint tools

CDC/RDC checkers

Synthesis tools

STA platforms

Job description

Synopsys, Inc. in Sunnyvale, CA seeks a senior architect to lead design teams through full ASIC/FPGA cycles, from specification to GDSII handoff.

You will partition complex SOCs, balance performance and power, and drive RTL using SystemVerilog while collaborating with verification, DFT, and physical design groups. You will implement PCIe, Ethernet, and UCIe in SOC designs, refine design flows, and work with customers across aerospace, automotive, and HPC markets.