Senior PHY & RTL Design Architect (DDR/UCIe)

Synopsys Inc; Boxborough (MA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Comprehensive benefits package

Competitive compensation

Job summary

Synopsys Inc. is seeking a highly experienced digital design engineer to lead RTL and PHY architecture for high-speed interfaces such as DDRIO and UCIe.

You will own ASIC design cycles from concept to implementation, mentor engineers, and collaborate with verification, physical design, and system teams to deliver scalable silicon solutions. You will influence architectural decisions, optimize for performance, power, area, and drive complex IP development across SERDES and DDR subsystems,

Qualifications

• BS in Electrical Engineering, Computer Engineering, or related field (12+ years of experience) OR MS with 10+ years of experience.
• Strong experience in ASIC RTL design and digital logic development.
• Expertise in PHY design, DDRIO, UCIe, SERDES, or related high-speed interfaces.
• Solid understanding of the complete SoC design cycle, from architecture to implementation.
• Experience with design verification methodologies and hardware debugging.

Responsibilities

• Architect, design, and develop high-performance digital logic for PHY, DDRIO, and UCIe-based solutions.
• Define and implement RTL architectures with verification, physical design, and system teams.
• Drive chip- and block-level design activities through all ASIC development phases.
• Optimize designs for performance, power, area (PPA), and scalability.
• Develop and evaluate complex physical IP solutions, including SERDES and DDR subsystems.
• Review designs and mentor engineers to ensure technical excellence.
• Collaborate with cross-functional teams to deliver silicon solutions on schedule.

Skills

ASIC RTL design

Digital logic development

PHY design

DDRIO

UCIe

SERDES

SoC design cycle

Design verification

Hardware debugging

Communication skills

Education

BS in Electrical Engineering or Computer Engineering

MS in EE/CE (optional)

Tools

EDA tools

Job description

Synopsys Inc. is seeking a highly experienced digital design engineer to lead RTL and PHY architecture for high-speed interfaces such as DDRIO and UCIe.

You will own ASIC design cycles from concept to implementation, mentor engineers, and collaborate with verification, physical design, and system teams to deliver scalable silicon solutions. You will influence architectural decisions, optimize for performance, power, area, and drive complex IP development across SERDES and DDR subsystems,