Senior SoC Architect & Technical Leader (ASIC/FPGA)

Synopsys Inc; Sunnyvale (CA); Presencial; USD 220.000 - 320.000; Jornada completa

Descripción de la vacante

Synopsys Inc. in Sunnyvale seeks a senior design leader to drive ASIC/FPGA programs from spec to silicon. You will lead teams, craft micro-architectures, and push for high-performance, low-power outcomes across automotive, aerospace, and HPC markets.

You’ll mentor engineers, resolve timing and CDC issues, and work directly with customers to translate requirements into robust turnkey designs using SystemVerilog and industry protocols.

Formación

• Bachelor's degree in Electrical Engineering or Computer Engineering.
• 15+ years designing and verifying ASIC/FPGA through multiple tape-outs or production releases.
• Proven experience leading design teams and mentoring engineers.
• Deep understanding of the full ASIC design flow from micro-architecture to handoff.
• Strong SystemVerilog RTL coding skills and ability to review complex control/datapath logic.
• Experience with PCIe, Ethernet, or UCIe in production designs.

Responsabilidades

• Lead design teams through full ASIC and FPGA development cycles, from specification to GDSII handoff.
• Partition and architect complex SOC designs from customer requirements, balancing performance, area, and power.
• Drive RTL development using SystemVerilog, ensuring quality through reviews, lint checks, CDC/RDC analysis, and synthesis readiness.
• Collaborate with verification, DFT, and physical design teams to resolve integration issues and timing closures.
• Implement complex industry-standard protocols including PCIe, Ethernet, and UCIe within SOC designs.
• Develop and refine ASIC design flows and methodologies using Synopsys and vendor tools for simulation, synthesis, static timing analysis, and signoff.
• Work hands-on with customers across automotive, aerospace, defense, and HPC markets.

Conocimientos

SystemVerilog RTL

Leadership

ASIC/FPGA design

Timing closure

Clock domain crossing

PCIe/Ethernet/UCIe protocols

Educación

Bachelor's degree in Electrical Engineering or Computer Engineering

Herramientas

Simulators

Lint tools

CDC/RDC checkers

Synthesis tools

STA platforms

Descripción del empleo

Synopsys Inc. in Sunnyvale seeks a senior design leader to drive ASIC/FPGA programs from spec to silicon. You will lead teams, craft micro-architectures, and push for high-performance, low-power outcomes across automotive, aerospace, and HPC markets.

You’ll mentor engineers, resolve timing and CDC issues, and work directly with customers to translate requirements into robust turnkey designs using SystemVerilog and industry protocols.