Senior SoC RTL Design Engineer

Synopsys Inc; Gilbert (AZ); On-site; USD 110,000 - 140,000; Full time

Benefits offered by this job

Health benefits

Competitive compensation

Job summary

Synopsys Inc. in Gilbert, AZ is seeking an RTL engineer to turn RTL specifications into robust Verilog/SystemVerilog designs for block‑level architectures, including state machines, pipelines, FIFOs, and memory controllers.

You will ensure clean synthesis and meet timing goals across the ASIC/FPGA flow. You will collaborate with verification, DFT, and physical design teams globally, write automation scripts (Python/Tcl), and participate in design reviews to communicate tradeoffs and decisions.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• 3 to 4 years of hands-on ASIC/FPGA RTL design, implementation, and debugging.
• Strong proficiency in Verilog/SystemVerilog/VHDL RTL coding for registers, pipelines, state machines, memories, and FIFOs.
• Understanding ASIC design flow from micro-architecture to RTL development, synthesis, and timing closure.

Responsibilities

• Write/Review Verilog, SystemVerilog, or VHDL RTL for block-level designs (state machines, pipelines, FIFOs, memory controllers).
• Run RTL quality checks using lint, CDC/RDC analysis, and synthesis.
• Collaborate with verification engineers to debug testbenches, refine corner cases, and close coverage gaps.
• Work with physical design teams to resolve timing issues and support timing closure from netlist through signoff.
• Implement standard interface protocols (AXI, APB, AHB, I2C, SPI) within SoC subsystems.
• Use Python/Tcl/Shell to automate repetitive design tasks.
• Participate in design reviews with global teams and communicate design decisions clearly.

Skills

Verilog/SystemVerilog

RTL design

Timing closure

ASIC/FPGA

Scripting (Python/Tcl)

Education

Bachelor's or Master's in Electrical Engineering or Computer Engineering

Tools

Simulators

Lint tools

CDC/RDC analysis tools

Synthesis tools

Static timing analysis

Job description

Synopsys Inc. in Gilbert, AZ is seeking an RTL engineer to turn RTL specifications into robust Verilog/SystemVerilog designs for block‑level architectures, including state machines, pipelines, FIFOs, and memory controllers.

You will ensure clean synthesis and meet timing goals across the ASIC/FPGA flow. You will collaborate with verification, DFT, and physical design teams globally, write automation scripts (Python/Tcl), and participate in design reviews to communicate tradeoffs and decisions.