Senior FPGA Prototyping & ProtoCompiler Lead

Synopsys Inc; Sunnyvale (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Synopsys, Inc. in Sunnyvale, CA, seeks an senior engineer to lead FPGA prototyping and advanced verification for billion-gate SoCs in AI, automotive, and data-center projects.

You will deploy HAPS-200 and ProtoCompiler, drive the ASIC-to-FPGA flow across partitioning, clocking, synthesis, and bring-up, and debug high-speed interfaces. You will partner with R&D and PM to shape features, mentor teams, and present at customer sites.

Qualifications

• Bachelor's/Master's/PhD in EE/CE/CS or equivalent hands-on experience.
• 10+ years in FPGA/ASIC development and verification.
• Deep expertise in FPGA synthesis, place-and-route, timing closure, and constraint development.
• Strong SystemVerilog, UVM, assertions, functional coverage, and testbench architecture.
• Hands-on experience with PCIe, DDR4/DDR5, LPDDR, Ethernet, AXI, CXL, or SerDes.
• Proficiency in Tcl, Python, or shell scripting for automation.
• Experience with Synopsys HAPS and ProtoCompiler; familiarity with ZeBu, Palladium, Protium, or Veloce is a plus.

Responsibilities

• Lead technical deployments of HAPS-200 and ProtoCompiler for strategic customers building billion-gate SoCs.
• Drive ASIC-to-FPGA flow including partitioning, clock conversion, synthesis, place-and-route, timing closure, and hardware bring-up on multi-FPGA systems.
• Debug complex interface IP subsystems including DDR4/DDR5, PCIe Gen3-6, CXL, UCIe, Ethernet, AXI, and SerDes architectures.
• Reproduce, analyze, and resolve critical RTL issues, partitioning failures, timing violations, protocol mismatches, and hardware bring-up failures.
• Collaborate with ProtoCompiler R&D and Product Management to validate new features and influence roadmap priorities.
• Develop reusable methodologies for partitioning strategies, clock architecture, debug instrumentation, and hardware/software co-validation.
• Mentor applications engineers globally, lead technical workshops and architecture reviews, and represent Synopsys at customer sites and conferences.

Skills

FPGA implementation

ASIC design

SystemVerilog

UVM

Scripting

Partitioning & clock domain crossing

Education

BS/MS/PhD in EE/CE/CS

Tools

Xilinx Vivado

Intel Quartus

Verdi

ProtoCompiler

HAPS

Job description

Synopsys, Inc. in Sunnyvale, CA, seeks an senior engineer to lead FPGA prototyping and advanced verification for billion-gate SoCs in AI, automotive, and data-center projects.

You will deploy HAPS-200 and ProtoCompiler, drive the ASIC-to-FPGA flow across partitioning, clocking, synthesis, and bring-up, and debug high-speed interfaces. You will partner with R&D and PM to shape features, mentor teams, and present at customer sites.